• Supports (per pixel) alpha-blending of seventeen video/graphics and logo layers video/graphics
• Optional logo (in block RAM) layer with color transparency support
• Layers can either be memory mapped AXI4 interface or AXI4-Stream
• Provides programmable background color
• Provides programmable layer position and size
• Provides upscaling of layers by 1x, 2x, or 4x
• Optional built-in color space conversion and chroma re-sampling
• Supports RGB, YUV 444, YUV 422, YUV 420
• Supports 8, 10, 12, and 16 bits per color component input and output on stream interface, 8-bit and 10-bit per color component on memory interface
• Supports semi-planar memory formats next to packed memory formats
• Supports spatial resolutions from 64 × 64 up to 8,192 × 4,320
• Supports 8K60 in all supported device families.
Note: Performance on low power devices might be lower .
• Supports Programmable CSC coefficients to support various calorimetry like BT601, BT709, and BT2020.
• Supports 1, 2, 4, or 8 samples per clock.
• Supports programmable CSC coefficient registers .
|
LogiCORE™ IP Facts Table |
|||||
|---|---|---|---|---|---|
|
Core Specifics |
|||||
|
Supported Device Family (1) |
AMD Versal ™ ACAP, AMD ltraScale+™ Families AMD UltraScale™ Architecture AMD Zynq ™ 7000 SoC 7 Series FPGAs |
||||
|
Supported User Interfaces |
AXI4-Master, AXI4-Lite, AXI4-Stream (2) |
||||
|
Resources |
|||||
|
Provided with Core |
|||||
|
Design Files |
Not Provided |
||||
|
Example Design |
Yes |
||||
|
Test Bench |
Not Provided |
||||
|
Constraints File |
Xilinx Design Constraints (XDC) |
||||
|
Simulation Model |
Encrypted RTL |
||||
|
Supported
|
Standalone DRM/KMS |
||||
|
Tested Design Flows (4) |
|||||
|
Design Entry |
AMD Vivado ™ Design Suite |
||||
|
Simulation |
For supported simulators, see the
|
||||
|
Synthesis |
Vivado Synthesis |
||||
|
Support |
|||||
|
Release Notes and Known Issues |
Master Answer Record: AR 66753 |
||||
|
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
||||
|
Notes: 1. For a complete list of supported devices, see the Vivado IP catalog. 2. Video protocol as defined in the AXI4-Stream Video IP and System Design Guide (UG934) [Ref 3] . 3. Standalone driver details can be found in <Install Directory>/Vitis/<Release>/data/embeddedsw/doc/xilinx_drivers_api_toc.htm. Linux OS and driver support information is available from the Wiki page .
4.
For the supported versions of the tools, see the
|
|||||