Table: Common Interface Signals summarizes the signals which are either shared by, or not part of the dedicated AXI4-Stream, memory mapped AXI4 data, or AXI4-Lite control interfaces.
|
Signal Name |
I/O |
Width |
Description |
|---|---|---|---|
|
ap_clk |
I |
1 |
Video core clock |
|
ap_rst_n |
I |
1 |
Video core active-Low reset |
|
interrupt |
O |
1 |
Interrupt Request Pin |
The ap_clk and ap_rst_n signals are shared between the core, the AXI4-Stream, memory mapped AXI4 data interfaces, and the AXI4-Lite control interface.