Layer Buffer Plane 1 (0x0#40) and Layer Plane 2 Buffer (0x0*4C) Registers - 5.2 English

Video Mixer LogiCORE IP Product Guide (PG243)

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5.2 English

In case the layer is a memory layer, the Layer Plane 1 Buffer register specifies the frame buffer address of plane 1. For the semi-planar formats (Y_UV8, Y_UV8_420, Y_UV10, and Y_UV10_420), the chroma buffer is specified by the Layer Plane 2 Buffer register. The addresses must be aligned to the data size of the memory mapped AXI4 interface. For the Video Mixer , the data size of the memory mapped AXI4 interface is 64 × Samples per Clock bits, that is, 64, 128, 256, and 512 bits for 1, 2, 4, and 8 samples per clock, respectively. These registers are not applicable when the layer is a streaming layer.