Port Descriptions - 6.0 English

The MIPI CSI-2 RX Subsystem I/O signals are described in the following table.

Table 1. Port Descriptions
Signal Name	Direction	Description
lite_aclk	Input	AXI clock
lite_aresetn	Input	AXI reset. Active-Low. This signal should be synchronous to lite_aclk.
S00_AXI*		AXI4-Lite interface, defined in the Vivado Design Suite: AXI Reference Guide (UG1037)
dphy_clk_200M	Input	Clock for D-PHY core. Must be 200 MHz.
video_aclk	Input	Subsystem clock
video_aresetn	Input	Subsystem reset. Active-Low. This signal should be synchronous to video_aclk.
AXI4-Stream Video Interface when Video Format Bridge is Present
video_out_tvalid	Output	Data valid
video_out_tready	Input	Slave ready to accept the data
video_out_tuser[n-1:0]	Output	n is based on TUSER width selected in the Vivado IDE
		95-80	CRC
		79-72	ECC
		71-70	Reserved
		69-64	Data Type
		63-48	Word Count
		47-32	Line Number
		31-16	Frame Number
		15-2	Reserved
		1	Packet Error
		0	Start of Frame
video_out_tlast	Output	End of line
video_out_tdata[n-1:0]	Output	Data n is based on the Data type and number of pixels selected in the Vivado IDE (see video_out Port Widthvideo_out Port Width).
video_out_tdest[9:0]	Output	9-4	Data Type
video_out_tdest[9:0]	Output	3-0	Virtual Channel Identifier (VC) The TDEST value stays constant throughout the line.
AXI4-Stream Interface when Embedded Non-image Interface is Selected
emb_nonimg_tdata[n-1:0]	Output	Data n is based on Data type selected in the Vivado IDE (see Embedded Non-Image AXI4-Stream Interface TDATA Widths).
emb_nonimg_tdest[3:0]	Output	Specifies the Virtual Channel Identifier (VC) value of the embedded non-image packet
emb_nonimg_tkeep[n/8-1:0]	Output	Specifies valid bytes
emb_nonimg_tlast	Output	End of line
emb_nonimg_tready	Input	Slave ready to accept data
emb_nonimg_tuser[95:0]	Output	95-80	CRC
		79-72	ECC
		71-70	Reserved
		69-64	Data Type
		63-48	Word Count
		47-32	Line Number
		31-16	Frame Number
		15-2	Reserved
		1	Packet Error
		0	Start of frame
emb_nonimg_tvalid	Output	Data valid
AXI4-Stream Interface when Video Format Bridge is Not Present
video_out_tdata[n-1:0]	Output	Data n is based on TDATA width selected in the Vivado IDE.
video_out_tdest[n-1:0]	Output	n is based on TDEST width selected in the Vivado IDE:
		9-4	Data type
		3-0	Virtual Channel Identifier (VC)
video_out_tkeep[n/8-1:0]	Output	Specifies valid bytes
video_out_tlast	Output	End of line
video_out_tready	Input	Slave ready to accept data
video_out_tuser[n-1:0]	Output	n is based on TUSER width selected in the Vivado IDE
		95-80	CRC
		79-72	ECC
		71-70	Reserved
		69-64	Data Type
		63-48	Word Count
		47-32	Line Number
		31-16	Frame Number
		15-2	Reserved
		1	Packet Error
		0	Start of frame
video_out_tvalid	Output	Data valid
Other Signals
csirxss_csi_irq	Output	Interrupt (active-High) from CSI-2 RX Controller
frame_rcvd_pulse_out	Output	High when the Frame End (FE) short packet is received for the frame_rcvd_pulse_out Output current frame
AMD 7 series FPGA
mipi_dphy_if	Output	DPHY interface
rxbyteclkhs	Output	PPI high-speed receive byte clock
system_rst_out	Output	Reset indication due to PLL reset (active-High)
dlyctrl_rdy_out	Output	Ready signal output from IDEALYCTRL, stating delay values are adjusted as per vtc changes
dlyctrl_rdy_in	Input	Ready signal input to IDELAYCTRL. Refer to “Include IDELAYCTRL in Core” in the Configuration TabConfiguration Tab for more details.
clk_300m	Input	300 MHz clock for IDELAYCTRL
UltraScale+ and Versal Adaptive SoC Shared Logic Outside the Subsystem
mipi_phy_if	Output	DPHY interface
rxbyteclkhs	Output	PPI high-speed receive byte clock
clkoutphy_out	Output	PHY serial clock
system_rst_out	Output	Reset indication due to PLL reset (active-High)
pll_lock_out	Output	PLL lock indication (active-High)
rxbyteclkhs_cnts_out	Output	Continuous PPI high-speed receive byte clock for line rates > 1500 Mb/s
UltraScale+ and Versal Adaptive SoC Shared Logic Inside the Subsystem
mipi_phy_if	Output	DPHY interface
bg<x>_pin<y>_nc	Input	Inferred bitslice ports. The core infers bitslice0 of a nibble for strobe propagation within the byte group; <x> indicates byte group (0,1,2,3); <y> indicates bitslice0 position (0 for the lower nibble, 6 for the upper nibble) RTL Design: There is no need to drive any data on these ports. IP integrator: These ports must be brought to the top level of the design to apply the constraints correctly. Pins are available only for AMD UltraScale+ families. BITSLICE defines a single I/O for UltraScale+, NIBBLESLICE defines a single I/O for Versal devices.
clkoutphy_in	Input	PHY serial clock
pll_lock_in	Input	PLL Lock indication
rxbyteclkhs	Output	PPI high-speed receive byte clock
rxbyteclkhs_cnts_in	Input	Continuous PPI high-speed receive byte clock for line rates > 1500 Mb/s
ext_mmcm_clk_in	Input	External mmcm clock when selected External mmcm for line rates >1500
ext_mmcm_lock_in	Input	External mmcm lock in when selected External MMCM for line rates > 1500
ext_mmcm_clk_out	Output	mmcm clock out when selected to use MMCM inside subsystem for line rates >1500
ext_mmcm_lock_out	Output	mmcm lock out when selected to use MMCM inside subsystem for line rates > 1500
CSI-2 Controller Register Interface Disabled
ctrl_core_en	Input	Enable the core to receive and process packets
active_lanes[1:0]	Input	Active lanes
ctrl_dis_in_prgs	Output	Indicates the CSI-2 RX Controller core disable is in progress
errsotsynchs_intr	Output	Interrupt output indicating SoT synchronization completely failed
errsoths_intr	Output	Interrupt output indicating SoT error detected
cl_stopstate_intr	Output	High when clock lane is currently in stop state
dl<n>_stopstate_intr	Output	High when the lane module is currently in stop state
crc_status_intr	Output	High when the computed CRC code is different from the received CRC code
ecc_status_intr[1:0]	Output	Bit 1- High when ECC syndrome is computed and two bits error is detected in the received packet header Bit 0- High when ECC syndrome was computed and a single bit error in the packet header was detected and corrected
linebuffer_full	Output	High when line buffer is full
The active-High reset for the MIPI D-PHY core is generated internally by setting the external active-Low reset (`video_aresetn` ) to 0. Each frame start packet with Virtual Channel (VC) identifier is mapped to the first image packet and the first embedded non-image with the corresponding VC. As CRC appears at the end of the MIPI packet, ECC, and CRC are reported ONLY during the last beat of the stream transfer when TLAST and TVALID are asserted. You need to ignore the ECC/CRC reported during other transfer beats. See Interface Debug for more details.