Example 2 - 6.0 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2024-05-30
Version
6.0 English

When the core is configured with RAW6 and two pixels per clock, the video_out port width is set to 16 bits. Within the 16 bits, the RAW6 and RAW8 pixels are aligned to the most significant bits as shown in the following table.

Table 1. Pixel Packing for RAW8 and RAW6 Data Types
Bit Positions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAW8 q7 q6 q5 q4 q3 q2 q1 q0 p7 p6 p5 p4 p3 p2 p1 p0
RAW6 q5 q4 q3 q2 q1 q0     p5 p4 p3 p2 p1 p0    
  1. p0 to p7 is the first pixel bits of RAW8; q0 to q7 is the second pixel bits of RAW8.
  2. p0 to p5 is the first pixel bits of RAW6; q0 to q5 is the second pixel bits of RAW6.