SP701 Application Example Design Overview - 6.0 English - PG232

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2024-11-13
Version
6.0 English

The Application Example Design demonstrates the usage of the MIPI CSI-2 RX Subsystem and MIPI DSI TX Subsystem on Spartan 7 SP701 board. On the capture path, the system receives images captured by pcam-5c image sensor. Processed images are displayed on either the HDMI monitor or MIPI DSI Display.

The MIPI CSI-2 RX Subsystem decodes, processes video data and presents on AXI4-Stream data with two pixels data per clock. The RAW video data is then converted into RGB data using the Demosaic IP two pixels at a time. The AXI4-Stream data is sent to the AXI Switch that broadcast the stream to MIPI DSI TX Subsystem or the AXI4-Stream to Video Out Subsystem depending on the user selection.

The Video Test Pattern Generator IP (V-TPG) is available in the HDMI Path to act as an alternate source of video in case no MIPI CSI-2 video source is present. The TPG (in pass-through mode) sends video packets across to the AXI4-Stream to Video Out.

If the MIPI DSI TX Subsystem path is chosen, the video is passed through a video processing subsystem configured as a Scaler. This is required as the MIPI DSI Panel works on a fixed resolution of 1920x1200. The video must be up scaled (1080p) to 1920x1200 resolution for the MIPI DSI display panel.