Latency - 6.0 English - PG232

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)
Document ID
PG232
Release Date
2024-11-13
Version
6.0 English

The CSI-2 RX Subsystem core latency is the time from the start-of-transmission (SoT) pattern on the serial lines to the tvalid signal assertion at CSI-2 RX Subsystem output. This includes the D-PHY latency, MIPI RX Controller latency and VFB latency (if the Video Format Bridge is included in the subsystem).

The following figure represents the latency calculation for the subsystem.

Figure 1. MIPI CSI-2 RX Subsystem Latency Calculation Page-1 Sheet.37 Process.507 MIPI CS12 RX SUBSYSTEM MIPI CSI2 RX SUBSYSTEM Process.507.3 D-PHY D-PHY Process.5 VFB VFB Process.507.6 rxbyteclk Domain rxbyteclk Domain Process.7 Video Clock Domain Video Clock Domain 8pt. Arial Text.508 Serial Lines Serial Lines 8pt. Arial Text.508.9 D-PHY Latency D-PHY Latency 8pt. Arial Text.10 Controller Latency Controller Latency 8pt. Arial Text.11 VFB Latency VFB Latency 8pt. Arial Text.508.12 PPI PPI 8pt. Arial Text.13 Streaming I/F Streaming I/F 8pt. Arial Text.14 Streaming I/F Streaming I/F Standard Arrow.509 Standard Arrow.16 Standard Arrow.17 Standard Arrow.18 Standard Arrow.19 Standard Arrow.20 Sheet.21 Sheet.22 Sheet.23 Process.4 MIPI CSI2 RX Controller MIPI CSI2 RXController Standard Arrow.22 Sheet.26 Sheet.27 Sheet.28 Standard Arrow.24 Standard Arrow.25 Standard Arrow.26 Sheet.32 X22862-050819 Sheet.33 Sheet.34 Sheet.35 Sheet.36 X22862-050819