The MIPI CSI-2 RX Subsystem MIPI D-PHY sub-core provides a Pin Assignment tab in the Vivado IDE to select the HP I/O bank. The clock lane and data lane(s) are implemented on the selected I/O bank BITSLICE(s).
Note: This tab is not available for AMD 7
series FPGA configurations.
Note: When placing multiple cores, follow banking rules for
the target architecture. For UltraScale+ designs,
multiple cores cannot target the same nibble (upper or lower). For more details refer to
UltraScale
Architecture SelectIO Resources User Guide (UG571).