I/O Planning - 6.0 English

The MIPI CSI-2 RX Subsystem provides an I/O planner feature for I/O selection. In the Pin Assignment tab, dedicated byte clocks (DBC) or quad byte clocks (QBC) are listed for the clock lane for the selected HP I/O bank. For the QBC clock lane, all of the I/O pins are listed for data lane I/O selection but for the DBC clock lane only the byte group I/O pins are listed for data lane I/O selection.

Eight MIPI CSI-2 RX Subsystem IP cores can be implemented per IO bank based on BITSLICE and BITSLICE_CONTROL instances in the UltraScale+ devices.

Note: If the RX data lane I/O pins are selected non-contiguously then an additional one, two, or three I/O pins (RX_BITSLICE) are automatically used for clock/Strobe propagation. Therefore, it is recommended that you select adjacent I/O pins for the RX configuration to make efficient use of the I/O. The propagation of strobes to the RX data pins follows the inter-byte and inter-nibble clocking rules given in the UltraScale Architecture SelectIO Resources User Guide (UG571). All lanes of a particular MIPI CSI-2 RX Subsystem instance need to be in the same HP IO bank which is automatically controlled by the Pin Assignment tab of the XGUI for UltraScale+ devices. Multiple MIPI CSI-2 RX Subsystem instances sharing clocking resources also need to be in the same HP IO bank.

The MIPI CSI-2 RX Subsystem GUI does not have an I/O Assignment tab for AMD Versal™ adaptive SoC. Instead you need to use consolidated I/O planning in the main Vivado IDE Planning, that is, nibble planner. You can select any I/O for the data lanes for the selected XPIO bank. For the clock lane, select the clock capable pin that is the 0 th pin of a nibble for the selected XPIO bank. Detailed steps on how to perform the Vivado IDE planning is detailed under section I/O Planning for Versal adaptive SoC Advanced IO Wizard in the Advanced I/O Wizard LogiCORE IP Product Guide (PG320).

While selecting IOs in a bank across nibbles, you need to ensure the Inter-nibble, Inter-byte clock guidelines are followed. See the “Clocking” section in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010). For more details on Versal adaptive SoC IO planning, see MIPI D-PHY LogiCORE IP Product Guide (PG202).

The following figure shows the eight MIPI CSI-2 RX Subsystem IP cores configured with one clock lane and two data lanes and implemented in a single HP/XP I/O bank.

The csi2_rx_master is configured with Include Shared Logic in core option and the remaining cores are configured with Include Shared Logic in example design. The constant clkoutphy signal is generated within the PLL of the csi2_rx_master core irrespective of line rate and is shared with all other slave IP cores (csi2_rx_slave1 to csi2_rx_slave7) with different line rates.

The controller and target cores can be configured with a different line rate when sharing clkoutphy within the IO bank.

Figure 1. MIPI CSI-2 RX Subsystem Core Shared Logic Use Case for Single I/O Bank

The maximum number of MIPI CSI-2 interfaces which can be connected to a single HP IO (UltraScale) or XPIO (Versal adaptive SoC) bank depends on the number of clock capable pins available on that bank.

Figure 2. Subsystem Customization Screen - Pin Assignment

I/O Planning - 6.0 English - PG232

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)