Core Overview - Core Overview - 6.0 English - PG232

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)
Document ID
PG232
Release Date
2025-11-20
Version
6.0 English

The MIPI CSI-2 RX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between MIPI-based image sensors and an image sensor pipe. An internal high speed physical layer design, D-PHY/C-PHY, is provided that allows direct connection to image sources. The top level customization parameters select the required hardware blocks needed to build the subsystem. The following figure shows the subsystem architecture.

Figure 1. Subsystem Architecture Page-1 Process AXI Crossbar AXI Crossbar Process.3 Video Format Bridge VideoFormatBridge Process.4 MIPI CSI-2 RX Controller MIPI CSI-2 RXController Process.5 MIPI D-PHY MIPI D-PHY Standard Arrow.6 Standard Arrow.7 Standard Arrow.10 Video Interface (AXI4-Stream) Video Interface(AXI4-Stream) Standard Arrow.11 Standard Arrow.15 Embedded Non-Image Interface (AXI4-Stream) Embedded Non-ImageInterface (AXI4-Stream) Standard Arrow.17 csirxss_csi_irq csirxss_csi_irq Standard Arrow.19 Serial Interface Serial Interface Double Arrow Vertical.14 AXI4-Lite Interface AXI4-Lite Interface Standard Arrow.12 PPI PPI Process.6 Standard Arrow.22 dphy_clk_200M dphy_clk_200M Standard Arrow.23 lite_aclk lite_aclk Standard Arrow.24 lite_aresetn lite_aresetn Standard Arrow.25 video_aclk video_aclk Standard Arrow.26 video_aresetn video_aresetn Sheet.20 X14819-031416 Sheet.28 Sheet.29 Sheet.30 Sheet.31 X14819-031416

The subsystem consists of the following sub-cores:

  • MIPI D-PHY / MIPI RX-PHY
  • MIPI CSI-2 RX Controller
  • AXI Crossbar/Smart Connect
  • Video Format Bridge