Generic Short Packet Register - 6.0 English

The Generic Short Packet register is described in the following table. Packets received with generic short packet codes are stored in a 31-deep internal FIFO and are made available through this register. The following conditions reset the FIFO:

• External reset on video_aresetn
• Core disable or soft reset through register settings.

Note the following:

1. If one-bit error occurs during data-transmission, the MIPI CSI-2 controller fixes the error-bit and stores generic short packet data into the FIFO.
2. When a short packet is received with a 2-bit error, the MIPI CSI-2 controller discards the data without pushing the data to the FIFO.
3. Because the data field of the register is only 16 bits wide, the ECC information is not stored.