Transfer Descriptor NXTDESC_PNTR (Next Descriptor Pointer

Transfer Descriptor NXTDESC_PNTR (Next Descriptor Pointer – Offset 00h) - 4.1 English

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)

Document ID

PG034

Release Date

2022-05-18

Version

4.1 English

This word provides the address pointer to the first word of the next transfer descriptor in the descriptor chain.

Figure 3-2: Transfer Descriptor NXTDESC_PNTR Word
X-Ref Target - Figure 3-2

Table 3-2: Transfer Descriptor NXTDESC_PNTR Word Details
Bits	Field Name	Description
31 to 6	NxtDescPntr	Next Descriptor Pointer. This field is an address pointer (most significant 26 bits) to the first word of the next transfer descriptor to be executed by the CDMA SG Engine. The least-significant 6 bits of this register are appended to this value when used by the SG Engine forcing transfer descriptors to be loaded in memory at 128-byte address alignment.
5 to 0	Reserved	These bits are reserved and fixed to zeros. This forces the address value programmed in this register to be aligned to 128-byte aligned addresses.