This register provides Tail Descriptor Pointer for the AXI CDMA Scatter Gather Descriptor Management.
Figure 2-6: TAILDESC_PNTR Register
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X-Ref Target - Figure 2-6
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Table 2-8: TAILDESC_PNTR Register Details
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Bits
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Field Name
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Default Value
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Access Type
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CDMA Mode Used
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Description
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31 to 6
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Tail Descriptor Pointer
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0
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R/W
(RO)
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SG
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Tail Descriptor Pointer. Indicates pause pointer for descriptor chain execution. The AXI CDMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer. Like Current descriptor, this too shall be 64byte aligned.
When the AXI CDMA is in SG Mode and the address space is 32 bits (CDMACR.SGMode = 1), a write by the software application to the TAILDESC_PNTR (in case of 32 bit mode) register causes the AXI CDMA SG Engine to start fetching descriptors starting from the CURDESC_PNTR register value. If the SG engine is paused at a tail pointer pause point, the SG engine restarts descriptor execution at the next sequential transfer descriptor. If the AXI CDMA is not idle (CDMASR.IDLE = 0), writing to the TAILDESC_PNTR has no effect except to reposition the SG pause point.
This register is cleared when CDMACR.SGMode = 0.
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5 to 0
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Reserved
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0
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RO
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N/A
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Writing to these bits has no effect and they are always read as zeros.
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Notes:
1.RO = Read Only. Writing has no effect.
2.R/W = Read/Write
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