Revision History - 4.1 English

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)

Document ID
PG034
Release Date
2022-05-18
Version
4.1 English

The following table shows the revision history for this document.

Date

Version

Description of Revisions

05/18/2022

4.1

Updated supported devices.

Updated Performance section links.

Updated Table: CURDESC_PNTR Register Details.

Updated Table: TAILDESC_PNTR Register Details.

Updated Table: TAILDESC_PNTR_MSB Register Details.

Updated Scatter Gather Mode.

04/04/2018

4.1

Updated the Enable CDMA Store and Forward option.

Updated Table 2-5.

04/05/2017

4.1

IP updated to support DRE for data widths up to 512 bits.

10/05/2016

4.1

Added a note about the AXI4-Lite write access register to the beginning of the Register Space section.

11/18/2015

4.1

Added support for UltraScale+ families.

09/30/2015

4.1

Added a note to Table 2-6, AXI CDMA Register Summary.

Added Appendix C, Additional Design Information.

04/01/2015

4.1

Added support for 64-bit addressing.

03/20/2013

1.1

Updated for Vivado 2013.1, Zynq-7000, and 7 Series FPGAs.

12/18/2013

4.1

Added UltraScale™ architecture support.

10/02/2013

4.1

Revision number advanced to 4.1 to align with core version number.

Added example design with implementation and test bench sections

Modified Bit 6 in CDMACR register to be Cyclic BD Enable.

Updated screen display in Chapter 4.

Added Cyclic CDMA Mode section to Chapter 3.

Added IP integrator content to Chapter 4.

03/20/2013

2.7

Updated for Vivado 2013.1 design tool.

Removed information pertaining to Series 6 FPGAs.

Updated IP Facts table.

Updated Figure 1-1, AXI CDMA Block Diagram and supporting text.

Updated Table 2-1 and 3-1

Updated Figure 4-1 and supporting text.

Updated Master Answer Records information and Contacting Technical Support and Debug Tools sections in Appendix B.

12/18/2012

2.6

Updated for Vivado 2012.4 and ISE v14.4 design tools.

Updated Table 2-1, Maximum Frequencies

Updated Debugging appendix.

Updated resource utilization tables: Tables 2-3, 2-4, and 2-5.

Removed Table 3-1, Reset Assertion/Deassertion Stabilization Times

Removed Parameter Descriptions section

Updated screen capture for Chapter 4 and removed one screen.

Removed material from the Output Generation section in Chapter 4 and updated the output hierarchy.

10/16/2012

2.5

Updated for Vivado 2012.3 and ISE v14.3 design tools.

Document clean up.

07/25/2012

2.0

Updated for Vivado 2012.2, Zynq features, and ISE v14.2

Added Vivado content in Customizing and Generating the Core

07/11/2012

1.1

Template update.

04/24/2012

1.0

Initial Xilinx Release

This new document is based on the LogiCORE IP AXI CDMA Product Specification (DS792).