Port Descriptions - 4.1 English

System Signals

m_axi_aclk

Clock

I

–

AXI CDMA Synchronization Clock

cdma_introut

Interrupt

O

0

Interrupt output for the AXI CDMA core

AXI4-Lite Slave Interface Signals

s_axi_lite_aclk

S_AXI_LITE

I

–

Synchronization clock for the AXI4-Lite interface. This clock can be the same as m_axi_aclk (synchronous mode) or different (asynchronous mode).

Note:   If it is asynchronous, the frequency of this clock must be less than or equal to the frequency of the m_axi_aclk.

s_axi_lite_aresetn

S_AXI_LITE

I

–

Active-Low AXI4-Lite Reset. When asserted Low, the AXI4-Lite Register interface and the entire CDMA core logic is put into hard reset. This signal must be synchronous to s_axi_lite_aclk.

s_axi_lite_*

S_AXI_LITE

I/O

–

See Appendix A of the Vivado AXI Reference Guide (UG1037)[Ref 2] for AXI4 signal.

CDMA Data AXI4 Read/Write Master Interface Signals

m_axi_*

M_AXI

I/O

–

See Appendix A of the Vivado AXI Reference Guide (UG1037) [Ref 2] for AXI4 signal.

Scatter Gather AXI4 Read/Write Master Interface Signals

m_axi_sg_*

M_AXI_SG

I/O

–

See Appendix A of the Vivado AXI Reference Guide (UG1037) [Ref 2] for AXI4 signal.

Notes:

1.The AXI CDMA IP does not use any of the ID pins of the AXI4 interfaces.

2.The IP wrapper/instantiation template has the ‘cdma_tvect_out’ port names. It is safe to keep these output pins open.