Feature Summary - 4.1 English - PG034

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)

Document ID
PG034
Release Date
2022-05-18
Version
4.1 English

Independent AXI4-Lite slave interface for register access.

°Fixed 32-bit data width

°Optional asynchronous operation mode

Independent AXI4 Master interface for the primary CDMA datapath. Parameterizable width of 32, 64, 128, 256, 512, and 1,024 bits with fixed-address burst (key hole) support.

Independent AXI4 Master interface for optional Scatter/Gather function. Fixed 32-bit data width.

Optional Data Realignment Engine for the primary CDMA datapath. Available for up to 512-bit datapath widths.

Provides Simple DMA only mode and an optional hybrid mode supporting both Simple DMA and Scatter Gather automation.

Support for up to 64-bit Address Space.