Register Details - 4.1 English

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)

Document ID: PG034
Release Date: 2022-05-18
Version: 4.1 English

AXI DMA v4.1 LogiCORE IP Product Guide (PG034)
IP Facts
Introduction
Features
Overview
Register Module
Scatter/Gather Block
DMA Controller
DataMover
Unaligned Transfers
Reset Module
Feature Summary
Applications
Licensing and Ordering
Product Specification
Standards
Performance
Throughput
Resource Utilization
Port Descriptions
Register Space
Endianess
Register Address Map
Register Details
CDMACR (CDMA Control – Offset 00h)
CDMASR (CDMA Status – Offset 04h)
CURDESC_PNTR (CDMA Current Descriptor Pointer – Offset 08h)
CURDESC_PNTR_MSB (CDMA Current Descriptor Pointer Offset – 0Ch)
TAILDESC_PNTR (CDMA Tail Descriptor Pointer – Offset 10h)
TAILDESC_PNTR_MSB (CDMA Tail Descriptor Pointer — Offset 14h)
SA (CDMA Source Address – Offset 18h)
SA_MSB (CDMA Source Address – Offset 1Ch)
DA (CDMA Destination Address – Offset 20h)
DA_MSB (CDMA Destination Address — Offset 24h)
BTT (CDMA Bytes to Transfer – Offset 28h)
Designing with the Core
Clocking
Resets
CDMA Lite Mode Restrictions
Programming Sequence
Scatter Gather Mode
Cyclic CDMA Mode
Transfer Descriptor Management
Scatter Gather Transfer Descriptor Definition
Transfer Descriptor NXTDESC_PNTR (Next Descriptor Pointer – Offset 00h)
Transfer Descriptor NXTDESC_PNTR_MSB (Next Descriptor Pointer – Offset 04h)
Transfer Descriptor SA Word (Source Address – Offset 08h)
Transfer Descriptor SA_MSB Word (Source Address — Offset 0Ch)
Transfer Descriptor DA Word (Destination Address – Offset 10h)
Transfer Descriptor DA_MSB Word (Destination Address — Offset 14h)
Transfer Descriptor CONTROL Word (Control – Offset 18h)
Transfer Descriptor Status Word (Status – Offset 1Ch)
Interrupts
SG Interrupt Threshold and Interrupt Coalescing
SG Delay Interrupt
Error Interrupts
Design Flow Steps
Customizing and Generating the Core
Vivado IP Catalog Options
Vivado IDE System Parameter
User Parameters
Output Generation
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Vivado Design Suite Debug Feature
Hardware Debug
Additional Design Information
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

Back to home page