Simulation Debug - 3.3 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID: PG210
Release Date: 2020-12-16
Version: 3.3 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Subsystem Overview
Feature Summary
25G Supported Features
10G Supported Features
10G/25G Runtime Switchable IP features
Applications
Licensing and Ordering
License Checkers
License Type
Ordering Information
Product Specification
Standards
Performance and Resource Utilization
Latency
Port Descriptions – MAC+PCS Variant
Transceiver Interface
AXI4-Stream Interface
AXI4-Stream Clocks and Resets
Transmit AXI4-Stream Interface
Data Lane Mapping - TX
Normal Transmission
Back-to-Back Continuous Transfers
Aborting a Transmission
Receive AXI4-Stream Interface
Data Lane Mapping - RX
Normal Frame Reception
Frame Reception with Errors
AXI4-Stream Control and Status Ports
Miscellaneous Status/Control Signals
Statistics Interface Ports
Pause Interface
Auto-Negotiation Ports
Link Training Ports
IEEE 802.3 Clause 74 FEC Interface
IEEE 802.3 Clause 108 RS-FEC Interface
Port Descriptions – PCS Variant
Transceiver Interface Ports
XGMII/25GMII Interface Ports
Miscellaneous Status/Control Ports
IEEE 802.3 Clause 74 FEC Interface
IEEE 802.3 Clause 108 RS-FEC Interface
Port Descriptions – 10G Ethernet MAC (64-bit) Variant
MII Interface
AXI4-Stream Interface
AXI4-Stream Interface - TX
Data Lane Mapping - TX
Normal Transmission
Aborting a Transmission
AXI4-Stream Interface – RX
Data Lane Mapping - RX
Normal Frame Reception
Frame Reception with Errors
AXI4-Stream Control and Status Ports - TX
AXI4-Stream Control and Status Ports - RX
Miscellaneous Status/Control Signals
Statistics Interface Ports
Pause Interface
Register Space
AXI4-Lite Ports
Configuration and Status Register Map
Configuration Register Map 10G/25G Ethernet Subsystem
Status Register Map for 10G/25G Ethernet Subsystem
Statistics Counters
Register Descriptions
Configuration Registers for 10G/25G Ethernet Subsystem
GT_RESET_REG: 0000
RESET_REG: 0004
MODE_REG: 0008
CONFIGURATION_TX_REG1: 000C
CONFIGURATION_RX_REG1: 0014
CONFIGURATION_RX_MTU: 0018
CONFIGURATION_VL_LENGTH_REG: 001C
TICK_REG: 0020
CONFIGURATION_REVISION_REG: 0024
CONFIGURATION_TX_TEST_PAT_SEED_A_LSB: 0028
CONFIGURATION_TX_TEST_PAT_SEED_A_MSB: 002C
CONFIGURATION_TX_TEST_PAT_SEED_B_LSB: 0030
CONFIGURATION_TX_TEST_PAT_SEED_B_MSB: 0034
CONFIGURATION_1588_REG: 0038
CONFIGURATION_TX_FLOW_CONTROL_REG1: 0040
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1: 0044
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2: 0048
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3: 004C
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4: 0050
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5: 0054
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1: 0058
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2: 005C
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3: 0060
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4: 0064
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5: 0068
CONFIGURATION_TX_FLOW_CONTROL_PPP_ETYPE_OP_REG: 006C
CONFIGURATION_TX_FLOW_CONTROL_GPP_ETYPE_OP_REG: 0070
CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_LSB: 0074
CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_MSB: 0078
CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_LSB: 007C
CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_MSB: 0080
CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_LSB: 0084
CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_MSB: 0088
CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_LSB: 008C
CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_MSB: 0090
CONFIGURATION_RX_FLOW_CONTROL_REG1: 0094
CONFIGURATION_RX_FLOW_CONTROL_REG2: 0098
CONFIGURATION_RX_FLOW_CONTROL_PPP_ETYPE_OP_REG: 009C
CONFIGURATION_RX_FLOW_CONTROL_GPP_ETYPE_OP_REG: 00A0
CONFIGURATION_RX_FLOW_CONTROL_GCP_PCP_TYPE_REG: 00A4
CONFIGURATION_RX_FLOW_CONTROL_PCP_OP_REG: 00A8
CONFIGURATION_RX_FLOW_CONTROL_GCP_OP_REG: 00AC
CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_LSB: 00B0
CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_MSB: 00B4
CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_LSB: 00B8
CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_MSB: 00BC
CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_LSB: 00C0
CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_MSB: 00C4
CONFIGURATION_RSFEC_REG: 00D0
CONFIGURATION_FEC_REG: 00D4
CONFIGURATION_AN_CONTROL_REG1: 00E0
CONFIGURATION_AN_CONTROL_REG2: 00E4
CONFIGURATION_AN_ABILITY: 00F8
CONFIGURATION_LT_CONTROL_REG1: 0100
CONFIGURATION_LT_TRAINED_REG: 0104
CONFIGURATION_LT_PRESET_REG: 0108
CONFIGURATION_LT_INIT_REG: 010C
CONFIGURATION_LT_SEED_REG0: 0110
CONFIGURATION_LT_COEFFICIENT_REG0: 0130
USER_REG_0: 0134
SWITCH_CORE_SPEED_REG: 0138
CONFIGURATION_1588_32BIT_REG: 0x013C
TX_CONFIGURATION_1588_REG: 0x0140
RX_CONFIGURATION_1588_REG: 0x0144
CONFIGURATION_TSN_REG: 0x019C
VERSAL_CHANNEL_NUM_REG: 0x014C
GT_WIZ_CHANNEL_LOOPBACK_REG: 0154
Status Registers for 10G/25G Ethernet Subsystem
STAT_TX_STATUS_REG1: 0400
STAT_RX_STATUS_REG1: 0404
STAT_STATUS_REG1: 0408
STAT_RX_BLOCK_LOCK_REG: 040C
STAT_RX_RSFEC_STATUS_REG: 043C
STAT_RX_FEC_STATUS_REG: 0448
STAT_TX_RSFEC_STATUS_REG: 044C
STAT_TX_FLOW_CONTROL_REG1: 0450
STAT_RX_FLOW_CONTROL_REG1: 0454
STAT_AN_STATUS: 0458
STAT_AN_ABILITY: 045C
STAT_AN_LINK_CTL: 0460
STAT_AN_LINK_CTL2: 09F0
STAT_LT_STATUS_REG1: 0464
STAT_LT_STATUS_REG2: 0468
STAT_LT_STATUS_REG3: 046C
STAT_LT_STATUS_REG4: 0470
STAT_LT_COEFFICIENT0_REG: 0474
STAT_RX_VALID_CTRL_CODE: 0494
STAT_CORE_SPEED_REG: 0498
STAT_TSN_REG: 0x049C
STAT_GT_WIZ_REG: 04A0
Statistics Counters
STATUS_CYCLE_COUNT_LSB: 0500
STATUS_CYCLE_COUNT_MSB: 0504
STAT_RX_FRAMING_ERR_LSB: 0648
STAT_RX_FRAMING_ERR_MSB: 064C
STAT_RX_BAD_CODE_LSB: 0660
STAT_RX_BAD_CODE_MSB: 0664
STAT_RX_ERROR_LSB: 0668
STAT_RX_ERROR_MSB: 066C
STAT_RX_RSFEC_CORRECTED_CW_INC_LSB: 0670
STAT_RX_RSFEC_CORRECTED_CW_INC_MSB: 0674
STAT_RX_RSFEC_UNCORRECTED_CW_INC_LSB: 0678
STAT_RX_RSFEC_UNCORRECTED_CW_INC_MSB: 067C
STAT_RX_RSFEC_ERR_COUNT0_INC_LSB: 0680
STAT_RX_RSFEC_ERR_COUNT0_INC_MSB: 0684
STAT_TX_FRAME_ERROR_LSB: 06A0
STAT_TX_FRAME_ERROR_MSB: 06A4
STAT_TX_TOTAL_PACKETS_LSB: 0700
STAT_TX_TOTAL_PACKETS_MSB: 0704
STAT_TX_TOTAL_GOOD_PACKETS_LSB: 0708
STAT_TX_TOTAL_GOOD_PACKETS_MSB: 070C
STAT_TX_TOTAL_BYTES_LSB: 0710
STAT_TX_TOTAL_BYTES_MSB: 0714
STAT_TX_TOTAL_GOOD_BYTES_LSB: 0718
STAT_TX_TOTAL_GOOD_BYTES_MSB: 071C
STAT_TX_PACKET_64_BYTES_LSB: 0720
STAT_TX_PACKET_64_BYTES_MSB: 0724
STAT_TX_PACKET_65_127_BYTES_LSB: 0728
STAT_TX_PACKET_65_127_BYTES_MSB: 072C
STAT_TX_PACKET_128_255_BYTES_LSB: 0730
STAT_TX_PACKET_128_255_BYTES_MSB: 0734
STAT_TX_PACKET_256_511_BYTES_LSB: 0738
STAT_TX_PACKET_256_511_BYTES_MSB: 073C
STAT_TX_PACKET_512_1023_BYTES_LSB: 0740
STAT_TX_PACKET_512_1023_BYTES_MSB: 0744
STAT_TX_PACKET_1024_1518_BYTES_LSB: 0748
STAT_TX_PACKET_1024_1518_BYTES_MSB: 074C
STAT_TX_PACKET_1519_1522_BYTES_LSB: 0750
STAT_TX_PACKET_1519_1522_BYTES_MSB: 0754
STAT_TX_PACKET_1523_1548_BYTES_LSB: 0758
STAT_TX_PACKET_1523_1548_BYTES_MSB: 075C
STAT_TX_PACKET_1549_2047_BYTES_LSB: 0760
STAT_TX_PACKET_1549_2047_BYTES_MSB: 0764
STAT_TX_PACKET_2048_4095_BYTES_LSB: 0768
STAT_TX_PACKET_2048_4095_BYTES_MSB: 076C
STAT_TX_PACKET_4096_8191_BYTES_LSB: 0770
STAT_TX_PACKET_4096_8191_BYTES_MSB: 0774
STAT_TX_PACKET_8192_9215_BYTES_LSB: 0778
STAT_TX_PACKET_8192_9215_BYTES_MSB: 077C
STAT_TX_PACKET_LARGE_LSB: 0780
STAT_TX_PACKET_LARGE_MSB: 0784
STAT_TX_PACKET_SMALL_LSB: 0788
STAT_TX_PACKET_SMALL_MSB: 078C
STAT_TX_BAD_FCS_LSB: 07B8
STAT_TX_BAD_FCS_MSB: 07BC
STAT_TX_UNICAST_LSB: 07D0
STAT_TX_UNICAST_MSB: 07D4
STAT_TX_MULTICAST_LSB: 07D8
STAT_TX_MULTICAST_MSB: 07DC
STAT_TX_BROADCAST_LSB: 07E0
STAT_TX_BROADCAST_MSB: 07E4
STAT_TX_VLAN_LSB: 07E8
STAT_TX_VLAN_MSB: 07EC
STAT_TX_PAUSE_LSB: 07F0
STAT_TX_PAUSE_MSB: 07F4
STAT_TX_USER_PAUSE_LSB: 07F8
STAT_TX_USER_PAUSE_MSB: 07FC
STAT_RX_TOTAL_PACKETS_LSB: 0808
STAT_RX_TOTAL_PACKETS_MSB: 080C
STAT_RX_TOTAL_GOOD_PACKETS_LSB: 0810
STAT_RX_TOTAL_GOOD_PACKETS_MSB: 0814
STAT_RX_TOTAL_BYTES_LSB: 0818
STAT_RX_TOTAL_BYTES_MSB: 081C
STAT_RX_TOTAL_GOOD_BYTES_LSB: 0820
STAT_RX_TOTAL_GOOD_BYTES_MSB: 0824
STAT_RX_PACKET_64_BYTES_LSB: 0828
STAT_RX_PACKET_64_BYTES_MSB: 082C
STAT_RX_PACKET_65_127_BYTES_LSB: 0830
STAT_RX_PACKET_65_127_BYTES_MSB: 0834
STAT_RX_PACKET_128_255_BYTES_LSB: 0838
STAT_RX_PACKET_128_255_BYTES_MSB: 083C
STAT_RX_PACKET_256_511_BYTES_LSB: 0840
STAT_RX_PACKET_256_511_BYTES_MSB: 0844
STAT_RX_PACKET_512_1023_BYTES_LSB: 0848
STAT_RX_PACKET_512_1023_BYTES_MSB: 084C
STAT_RX_PACKET_1024_1518_BYTES_LSB: 0850
STAT_RX_PACKET_1024_1518_BYTES_MSB: 0854
STAT_RX_PACKET_1519_1522_BYTES_LSB: 0858
STAT_RX_PACKET_1519_1522_BYTES_MSB: 085C
STAT_RX_PACKET_1523_1548_BYTES_LSB: 0860
STAT_RX_PACKET_1523_1548_BYTES_MSB: 0864
STAT_RX_PACKET_1549_2047_BYTES_LSB: 0868
STAT_RX_PACKET_1549_2047_BYTES_MSB: 086C
STAT_RX_PACKET_2048_4095_BYTES_LSB: 0870
STAT_RX_PACKET_2048_4095_BYTES_MSB: 0874
STAT_RX_PACKET_4096_8191_BYTES_LSB: 0878
STAT_RX_PACKET_4096_8191_BYTES_MSB: 087C
STAT_RX_PACKET_8192_9215_BYTES_LSB: 0880
STAT_RX_PACKET_8192_9215_BYTES_MSB: 0884
STAT_RX_PACKET_LARGE_LSB: 0888
STAT_RX_PACKET_LARGE_MSB: 088C
STAT_RX_PACKET_SMALL_LSB: 0890
STAT_RX_PACKET_SMALL_MSB: 0894
STAT_RX_UNDERSIZE_LSB: 0898
STAT_RX_UNDERSIZE_MSB: 089C
STAT_RX_FRAGMENT_LSB: 08A0
STAT_RX_FRAGMENT_MSB: 08A4
STAT_RX_OVERSIZE_LSB: 08A8
STAT_RX_OVERSIZE_MSB: 08AC
STAT_RX_TOOLONG_LSB: 08B0
STAT_RX_TOOLONG_MSB: 08B4
STAT_RX_JABBER_LSB: 08B8
STAT_RX_JABBER_MSB: 08BC
STAT_RX_BAD_FCS_LSB: 08C0
STAT_RX_BAD_FCS_MSB: 08C4
STAT_RX_PACKET_BAD_FCS_LSB: 08C8
STAT_RX_PACKET_BAD_FCS_MSB: 08CC
STAT_RX_STOMPED_FCS_LSB: 08D0
STAT_RX_STOMPED_FCS_MSB: 08D4
STAT_RX_UNICAST_LSB: 08D8
STAT_RX_UNICAST_MSB: 08DC
STAT_RX_MULTICAST_LSB: 08E0
STAT_RX_MULTICAST_MSB: 08E4
STAT_RX_BROADCAST_LSB: 08E8
STAT_RX_BROADCAST_MSB: 08EC
STAT_RX_VLAN_LSB: 08F0
STAT_RX_VLAN_MSB: 08F4
STAT_RX_PAUSE_LSB: 08F8
STAT_RX_PAUSE_MSB: 08FC
STAT_RX_USER_PAUSE_LSB: 0900
STAT_RX_USER_PAUSE_MSB: 0904
STAT_RX_INRANGEERR_LSB: 0908
STAT_RX_INRANGEERR_MSB: 090C
STAT_RX_TRUNCATED_LSB: 0910
STAT_RX_TRUNCATED_MSB: 0914
STAT_RX_TEST_PATTERN_MISMATCH_LSB: 0918
STAT_RX_TEST_PATTERN_MISMATCH_MSB: 091C
STAT_FEC_INC_CORRECT_COUNT_LSB: 0920
STAT_FEC_INC_CORRECT_COUNT_MSB: 0924
STAT_FEC_INC_CANT_CORRECT_COUNT_LSB: 0928
STAT_FEC_INC_CANT_CORRECT_COUNT_MSB: 092C
STAT_TX_MM_STATUS_LSB: 0x0980
STAT_TX_MM_STATUS_MSB: 0x0984
STAT_TX_MM_STATUS_LSB: 0x0988
STAT_TX_MM_FRAGMENT_MSB: 0x098C
STAT_TX_MM_HOLD_LSB: 0x0990
STAT_TX_MM_HOLD_MSB: 0x0994
STAT_RX_MM_ASSEMBLY_ERROR_LSB: 0x0998
STAT_RX_MM_ASSEMBLY_ERROR_MSB: 0x099C
STAT_RX_MM_FRAME_SMD_ERROR_LSB: 0x09A0
STAT_RX_MM_FRAME_SMD_ERROR_MSB: 0x09A4
STAT_RX_MM_FRAME_ASSEMBLY_OK_LSB: 0x09A8
STAT_RX_MM_FRAME_ASSEMBLY_OK_MSB: 0x09AC
STAT_RX_MM_FRAGMENT_LSB: 0x09B0
STAT_RX_MM_FRAGMENT_MSB: 0x09B4
Designing with the Subsystem
Clocking
PCS/PMA 64-bit Clocking
PCS/PMA 32-bit Clocking
10G/25G MAC with PCS/PMA Clocking
10 MAC-only Clocking
Low Latency 32-bit 10 Gb/s MAC with PCS
Low Latency 10G/25G MAC with PCS/PMA Clocking
Auto-Negotiation and Link Training Clocking
Resets
Component Support Layer Resets
Wrapper Resets
LogiCORE Example Design Clocking and Resets
Detailed Diagram of Single Core - Asynchronous Clock Mode (UltraScale/UltraScale+)
Detailed Diagram of Multiple Cores - Asynchronous Clock Mode (UltraScale/UltraScale+)
Detailed Diagram of Single Core (Versal)
Support for IEEE Standard 1588v2
Overview
Egress
Ingress
Port Descriptions
IEEE 1588v2 PTP Functional Description
Performance
RS-FEC Support
Overview
Port Descriptions
RS-FEC Functional Description
Ethernet Datapath Parity
802.1cm Preemption Feature
Features
Overview
Product Specification
Transmit AXI4-Stream Interface
Frame Transmission
Receive AXI4-Stream Interface
Frame Reception
Status/Control Interface
stat_rx_framing_err and stat_rx_framing_err_valid
stat_rx_block_lock
stat_rx_local_fault
RX Error Status
stat_rx_bad_fcs[1:0]
stat_rx_bad_code
Pause Processing
TX Pause Generation
RX Pause Termination
Auto-Negotiation
Auto-Negotiation
Overview
Functional Description
Link Training
Transmit
Frame Marker
Coefficient and Status
Training Sequence
Receive
Frame Lock State Machine
Received Data
Board Testing Steps for Auto-Negotiation and Link Training Using AXI4-Lite Interface
Design Flow Steps
Customizing and Generating the Subsystem
Configuration Tab
MAC Options Tab
GT Selection and Configuration Tab
Shared Logic Tab
Output Generation
Constraining the Subsystem
Simulation
Simulation Speed Up
Synthesis and Implementation
Example Design
Overview
Example Design Hierarchy (GT in Example Design)
User Interface
Core xci Top Level Port List
Common Clock/Reset Signals
Common Transceiver Interface Ports
Transceiver Core and Status Debug Ports
AXI4-Lite Interface Ports
AXI4-Stream User Interface Signals
MII User Interface Signals
TX Path Control/Status/Statistics Signals
RX Path Control/Status/Statistics Signals
TX Pause Interface Control/Status/Statistics Signals
RX Pause Interface Control/Status/Statistics Signals
IEEE 1588 TX/RX Interface Control/Status/Statistics Signals
AN and LT Interface Control/Status/Statistics Signals
Clause 74 FEC Interface Control/Status/Statistics Signals
IEEE Clause 108 (RS-FEC) Control/Status/Statistics Signals
PLL and SYS Clock
Duplex Mode of Operation
Runtime Switchable
Shared Logic Implementation
AXI4-Lite Interface Implementation
.h Header File
AXI4 Interface User Logic
IEEE Clause 108 (RS-FEC) Integration
PTP 1588 Timer Syncer IP
Introduction
Features
Core Overview
External ToD Interface Sub Block
PTP System Timer Sub Block
PTP Port Timer Sub Block
Port Descriptions
Timer Syncer IP Interface Ports
Clock Reset
External ToD Bus Interface
Per-Port Port Timer Interface
AXI4-Lite Interface
Internal Sub-Block Ports
External ToD Bus Ports
PTP System Timer Ports
Port Timer Ports
Register Space
Register Access Type Definitions
Register Map
Port Timer Registers
Software Driver Core Initialization
Instantiating the IP
Batch Mode Test Bench
Upgrading
Changes from v2.3 to v2.4
Ports Added
Registers Added
Ports Added
Changes from v2.3 (10/04/2017) to v2.3 (12/20/2017)
Ports Added
Port Changes
Ports Removed
Changes from v2.2 to v2.3
Ports Added
Ports Updated
Ports Removed
Port Name Changes
Registers
Changes from v2.1 to v2.2
Ports
Changes from v2.0 to v2.1
New Variants for 10 Gb/s Operation
Feature Updates for 25 Gb/s Operation
Ports
Changes from v2.0 (10/05/2016) to v2.0 (11/30/2016) version
Migrating from the Legacy XGEMAC
Port/Signal Comparison
Debugging
Finding Help on Xilinx.com
Documentation
Solution Centers
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Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Simulation Debug
Simulator License Availability
Slow Simulation
Simulation Fails Before Completion
Simulation Completes But Fails
Hardware Debug
General Checks
Timing
Transceiver Specific Checks
Ethernet Specific Checks
Signal Integrity
N/P Swapping
Clocking and Resets
RX Debug
TX Debug
Protocol Interface Debug
Diagnostic Signals
Statistics Counters
Debugging Auto-Negotiation and Link Training
Debugging Auto-Negotiation and Link Training Using the AXI4-Lite Interface
Additional Resources and Legal Notices
Xilinx Resources
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References
Revision History
Please Read: Important Legal Notices

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