Instantiating the IP - 3.3 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID

PG210

Release Date

2020-12-16

Version

3.3 English

The Timer Syncer IP is a hidden IP and therefore you need to use the following Tcl commands for instantiating the IP:

```
create_bd_design "design_1"
```
```
set_param bd.skipSupportedIPCheck true
```

set ptp_1588_timer_syncer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ptp_1588_timer_syncer ptp_1588_timer_syncer_0 ]

set_property -dict [ list \
CONFIG.AXI4LITE_FREQ {100.00} \
CONFIG.CORE_MODE {Timer_Syncer} \
CONFIG.ENABLE_EXT_TOD_BUS {0} \
CONFIG.ENABLE_HIGH_MODE {1} \
CONFIG.NUM_PORTS {1} \
CONFIG.TIMER_FORMAT {Time_of_Day} \
CONFIG.TS_CLK_PERIOD {4.0} \
] $ptp_1588_timer_syncer_0

Note: TS_CLK_PERIOD : 4.0 (250MHz).

```
startgroup
```

make_bd_pins_external  [get_bd_cells ptp_1588_timer_syncer_0] -quiet

make_bd_intf_pins_external [get_bd_cells ptp_1588_timer_syncer_0] -quiet

```
endgroup
```
```
assign_bd_address
```
```
validate_bd_design
```
```
save_bd_design
```
Click Create HDL Wrapper.
```
update_compile_order -fileset sources_1
```
Instantiate the design_1_wrapper() in the design and connect it appropriately with the Ethernet IP and AXI4-Lite interface.
Note: When you select Enable Timestamping Logic from the GUI Tab-2 of the XXV ethernet IP, the Timer Syncer IP is generated automatically and appropriately connected in the example design. For reference, you can generate example design of the XXV Ethernet IP core.