The following table shows the miscellaneous status/control ports.
| Name | I/O | Clock Domain | Description |
|---|---|---|---|
| dclk | I | Refer to Clocking. | Dynamic Reconfiguration Port (DRP) clock input. The required frequency is set by providing the value in the GT DRP Clock field in the Vivado® IDE GT Selection and Configuration tab. This must be a free running input clock. |
| ctl_local_loopback | I | Async | When High, this signal places the transceiver into the PMA loopback state. |