Ports in this section are available when Enable RX Flow Control Logic is selected from the MAC Options tab and Select Core is Ethernet MAC+PCS/PMA 64/32-bit.
| Name | Size | I/O | Description |
|---|---|---|---|
| ctl_rx_forward_control_* | 1 | I | A value of 1 indicates that the CORE forwards control packets to you. A value of 0 causes CORE to drop control packets. 1 |
| ctl_rx_pause_ack_* | 9 | I | Pause acknowledge signal. This bus is used to acknowledge the receipt of the pause frame from the user logic. |
| ctl_rx_check_ack_* | 1 | I | Wait for acknowledge. If this input is set to 1, the CORE uses the ctl_rx_pause_ack[8:0] bus for pause processing. If this input is set to 0, ctl_rx_pause_ack[8:0] is not used. 1 |
| ctl_rx_pause_enable_* | 9 | I | RX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority. 1 1 |
| ctl_rx_enable_gcp_* | 1 | I | A value of 1 enables global control packet processing. 1 |
| ctl_rx_check_mcast_gcp_* | 1 | I | A value of 1 enables global control multicast destination address processing. 1 |
| ctl_rx_check_ucast_gcp_* | 1 | I | A value of 1 enables global control unicast destination address processing. 1 |
| ctl_rx_pause_da_ucast_* | 48 | I | Unicast destination address for pause processing. 1 |
| ctl_rx_check_sa_gcp_* | 1 | I | A value of 1 enables global control source address processing. 1 |
| ctl_rx_pause_sa_* | 48 | I | Source address for pause processing. 1 |
| ctl_rx_check_etype_gcp_* | 1 | I | A value of 1 enables global control ethertype processing. 1 |
| ctl_rx_etype_gcp_* | 16 | I | Ethertype field for global control processing. 1 |
| ctl_rx_check_opcode_gcp_* | 1 | I | A value of 1 enables global control opcode processing. 1 |
| ctl_rx_opcode_min_gcp_* | 16 | I | Minimum global control opcode value. 1 |
| ctl_rx_opcode_max_gcp_* | 16 | I | Maximum global control opcode value. 1 |
| ctl_rx_enable_pcp_* | 1 | I | A value of 1 enables priority control packet processing. 1 |
| ctl_rx_check_mcast_pcp_* | 1 | I | A value of 1 enables priority control multicast destination address processing. 1 |
| ctl_rx_check_ucast_pcp_* | 1 | I | A value of 1 enables priority control unicast destination address processing. 1 |
| ctl_rx_pause_da_mcast_* | 48 | I | Multicast destination address for pause processing. 1 |
| ctl_rx_check_sa_pcp_* | 1 | I | A value of 1 enables priority control source address processing. 1 |
| ctl_rx_check_etype_pcp_* | 1 | I | A value of 1 enables priority control ethertype processing. 1 |
| ctl_rx_etype_pcp_* | 16 | I | Ethertype field for priority control processing. 1 |
| ctl_rx_check_opcode_pcp_* | 1 | I | A value of 1 enables priority control opcode processing. 1 |
| ctl_rx_opcode_min_pcp_* | 16 | I | Minimum priority control opcode value. 1 |
| ctl_rx_opcode_max_pcp_* | 16 | I | Maximum priority control opcode value. 1 |
| ctl_rx_enable_gpp_* | 1 | I | A value of 1 enables global pause packet processing. 1 |
| ctl_rx_check_mcast_gpp_* | 1 | I | A value of 1 enables global pause multicast destination address processing. 1 |
| ctl_rx_check_ucast_gpp_* | 1 | I | A value of 1 enables global pause unicast destination address processing. 1 |
| ctl_rx_check_sa_gpp_* | 1 | I | A value of 1 enables global pause source address processing. 1 |
| ctl_rx_check_etype_gpp_* | 1 | I | A value of 1 enables global pause ethertype processing. 1 |
| ctl_rx_etype_gpp_* | 16 | I | Ethertype field for global pause processing. 1 |
| ctl_rx_check_opcode_gpp_* | 1 | I | A value of 1 enables global pause opcode processing. 1 |
| ctl_rx_opcode_gpp_* | 16 | I | Global pause opcode value. 1 |
| ctl_rx_enable_ppp_* | 1 | I | A value of 1 enables priority pause packet processing. 1 |
| ctl_rx_check_mcast_ppp_* | 1 | I | A value of 1 enables priority pause multicast destination address processing. 1 |
| ctl_rx_check_ucast_ppp_* | 1 | I | A value of 1 enables priority pause unicast destination address processing. 1 |
| ctl_rx_check_sa_ppp_* | 1 | I | A value of 1 enables priority pause source address processing. 1 |
| ctl_rx_check_etype_ppp_* | 1 | I | A value of 1 enables priority pause ethertype processing. 1 |
| ctl_rx_etype_ppp_* | 16 | I | Ethertype field for priority pause processing. 1 |
| ctl_rx_check_opcode_ppp_* | 1 | I | A value of 1 enables priority pause opcode processing. 1 |
| ctl_rx_opcode_ppp_* | 16 | I | Priority pause opcode value. 1 |
| stat_rx_unicast_* | 1 | O | Increment for good unicast packets. |
| stat_rx_multicast_* | 1 | O | Increment for good multicast packets. |
| stat_rx_broadcast_* | 1 | O | Increment for good broadcast packets. |
| stat_rx_vlan_* | 1 | O | Increment for good 802.1Q tagged VLAN packets. |
| stat_rx_pause_* | 1 | O | Increment for 802.3x Ethernet MAC Pause packet with good FCS. |
| stat_rx_user_pause_* | 1 | O | Increment for priority-based pause packets with good FCS. |
| stat_rx_inrangeerr_* | 1 | O | Increment for packets with Length field error but with good FCS. |
| stat_rx_pause_valid_* | 9 | O | This bus indicates that a pause packet was received and the associated quanta on the stat_rx_pause_quanta[8:0][15:0] bus is valid and must be used for pause processing. If an 802.3x Ethernet MAC Pause packet is received, bit[8] is set to 1. |
| stat_rx_pause_quanta0_* | 16 | O | These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |
| stat_rx_pause_quanta1_* | 16 | O | These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |
| stat_rx_pause_quanta2_* | 16 | O | These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |
| stat_rx_pause_quanta3_* | 16 | O | These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |
| stat_rx_pause_quanta4_* | 16 | O | These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |
| stat_rx_pause_quanta5_* | 16 | O | These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |
| stat_rx_pause_quanta6_* | 16 | O | These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |
| stat_rx_pause_quanta7_* | 16 | O | These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |
| stat_rx_pause_quanta8_* | 16 | O | These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |
| stat_rx_pause_req_* | 9 | O | Pause request signal. When the RX receives a valid pause frame, it sets the corresponding bit of this bus to a 1 and keep it at 1 until the pause packet has been processed. |
|
|||