IEEE 1588 TX/RX Interface Control/Status/Statistics Signals - 3.3 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID: PG210
Release Date: 2020-12-16
Version: 3.3 English

Table 1. IEEE 1588 TX/RX Interface Control/Status/Statistics Signals
Name	Size	I/O	Description
ctl_tx_systemtimerin_*	80	I	System timer input for the TX. In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds. In transparent clock mode, bit 63 is expected to be zero, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions. This input must be in the TX clock domain.
ctl_rx_systemtimerin_*	80	I	System timer input for the RX. In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds. In transparent clock mode, bit 63 is expected to be zero, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions. This input must be in the same clock domain as the lane 0 RX SerDes.
ctl_tx_ptp_1step_enable_*	1	I	When set to 1, this bit enables 1-step operation.
ctl_tx_ptp_latency_adjust_*	11	I	This bus can be used to adjust the 1-step TX timestamp with respect to the 2-step timestamp. The units of bits [10:3] are nanoseconds and bits [2:0] are fractional nanoseconds. Note: This port is available when Include AXI4-Lite is not selected in the Configuration tab.
ctl_ptp_transpclk_mode_*	1	I	When set to 1, this input places the timestamping logic into transparent clock mode. In this mode,the system timer input is interpreted as a correction value. The TX will add the correction value to the TX timestamp according to the process defined in IEEE 1588v2. The sign bit of the correction value is assumed to be 0 (positive time). It is expected that the corresponding incoming PTP packet correction field has already been adjusted with the proper RX timestamp. Note: This port is available when Include AXI4-Lite is not selected in the Configuration tab.
stat_tx_ptp_fifo_read_error_*	1	O	Transmit PTP FIFO write error. A value of 1 on this status indicates that an error occurred during the PTP Tag write. A TX Path reset is required to clear the error.
stat_tx_ptp_fifo_write_error_*	1	O	Transmit PTP FIFO read error. A value of 1 on this status indicates that an error occurred during the PTP Tag read. A TX Path reset is required to clear the error.
tx_ptp_1588op_in_*	2	I	2'b00 – "No operation": no timestamp will be taken and the frame will not be modified. 2’b01 – “1-step”: a timestamp should be taken and inserted into the frame. 2’b10 – “2-step”: a timestamp should be taken and returned to the client using the additional ports of 2-step operation. The frame itself will not be modified. 2’b11 – Reserved: act as “No operation”.
tx_ptp_tag_field_in_*	16	I	The usage of this field is dependent on the 1588 operation For “No operation”, this field will be ignored. For “1-step” and “2-step” this field is a tag field. This tag value will be returned to the client with the timestamp for the current frame using the additional ports of 2-step operation. This tag value can be used by software to ensure that the timestamp can be matched with the PTP frame that it sent for transmission.
tx_ptp_tstamp_valid_out_*	1	O	This bit indicates that a valid timestamp is being presented on the TX.
tx_ptp_tstamp_tag_out_*	16	O	Tag output corresponding to tx_ptp_tag_field_in[15:0].
tx_ptp_tstamp_out_*	80	O	Timestamp for the transmitted packet SOP corresponding to the time at which it passed the capture plane. The representation of the bits contained in this bus is the same as the timer input.
rx_ptp_tstamp_valid_out_*	1	O	This bit indicates that a valid timestamp is being presented on the RX. This will be present only when core is Ethernet MAC+PCS/PMA-32/64-bit.
rx_ptp_tstamp_out_*	80	O	Timestamp for the received packet SOP corresponding to the time at which it passed the capture plane. Note that this signal will be valid starting at the same clock cycle during which the SOP is asserted for one of the segments. The representation of the bits contained in this bus is the same as the timer input.
tx_ptp_upd_chksum_in_*	1	I	TX UPD checksum value. Note: This port is available when PTP Operation mode is selected as one-step in MAC options tab.
tx_ptp_tstamp_offset_in_*	16	I	TX PTP timestamp offset. Note: This port is available when PTP Operation mode is selected as one-step in MAC options tab. Only even values are supported.
tx_ptp_chksum_offset_in_*	16	I	TX PTP check sum offset. Note: This port is available when PTP Operation mode is selected as one-step in MAC options tab. Only even values are supported.
tx_ptp_rxtstamp_in_*	64	I	TX PTP RX timestamp. Note: This port is available when PTP Operation mode is selected as one step in MAC options tab.