XGMII/25GMII Interface Ports - 3.3 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID: PG210
Release Date: 2020-12-16
Version: 3.3 English

The following table shows the XGMII/25GMII I/O ports.

Table 1. XGMII/25GMII Interface Ports
Name	I/O	Clock Domain	Description
rx_mii_d[63:0]	O	rx_mii_clk	Receive XGMII/25GMII Data bus.
rx_mii_c[7:0]	O	rx_mii_clk	Receive XGMII/25GMII Control bus.
rx_mii_clk	I	Refer to Clocking.	Receive XGMII/25GMII Clock input.
tx_mii_d[63:0]	I	tx_mii_clk	Transmit XGMII/25GMII Data bus.
tx_mii_c[7:0]	I	tx_mii_clk	Transmit XGMII/25GMII Control bus.
rx_clk_out	O	Refer to Clocking.	This is the reference clock for RX PCS stats.
tx_clk_out (or tx_mii_clk)	O	Refer to Clocking.	This output is used to clock the TX MII bus. Data is clocked on the positive edge of this signal.
rx_mii_reset	I	Async	Reset input for the RX MII interface.
tx_mii_reset	I	Async	Reset input for the TX MII interface.