AXI4-Stream Interface - 3.3 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID: PG210
Release Date: 2020-12-16
Version: 3.3 English

The AXI4-Stream interface clock and reset signals are shown in the following table.

Table 1. AXI4-Stream - Clocks and Resets
Name	I/O	Clock Domain	Description
rx_reset	I	Async	Reset for the RX circuits. This signal is active-High (1=Reset) and must be held High until the clock, clk is stable. The core handles synchronizing the rx_reset input to the appropriate clock domains within the core.
tx_reset	I	Async	Reset for the TX circuits. This signal is active-High (1=Reset) and must be held High until the clock, clk is stable. The core handles synchronizing the tx_reset input to the appropriate clock domains within the core.
clk	I		All signals between the 10G/25G High Speed Ethernet Subsystem and the user-side logic are synchronized to the positive edge of this signal.