Ethernet Datapath Parity - 3.3 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2020-12-16
Version
3.3 English

The Datapath Parity Feature provides soft error detection on datapath logic that resides between the core AXI4-Stream interface and the Ethernet FCS logic.

For each byte of the datapath, a single bit is provided that reflects the calculated parity of that byte.

Important: The IP core implements even parity such that the sum of all ones in the datapath including the parity bit results in an even number (i.e., 0, 2, 4..).

Datapath parity is implemented in both transmit and receive directions of the core datapath. In both directions, parity bits are considered valid only on valid AXI4-Stream bytes. More specifically, an AXI4-Stream byte is considered valid on cycles where TKEEP[n], TVALID and TREADY are all asserted. Parity bits associated with invalid AXI4-Stream bytes in the receive datapath should be ignored. Parity bits associated with AXI4-Stream invalid bytes in the transmit direction are not checked.

The Datapath Parity Feature adds a single statistic, stat_tx_bad_parity, to identify if a soft error has been detected. The statistic is clock-cycle based such that it can assert multiple times for a single packet. And, because it is clock cycle based, it identifies only that at least one soft error has been detected. If two soft errors are detected on a single clock cycle, only one soft error will be indicated. The presence of parity errors can also trigger the assertion of stat_tx_bad_fcs errors depending on the configuration.

For variants supporting parity, there is no configuration required for the receive datapath as all packets presented on the AXI4-Stream interface will have parity generated. In the transmit direction, the following table describes configuration bits that affect the behavior of the parity logic:

Table 1. Configuration Bits Affecting Parity Logic Behavior
ctl_tx_fcs_ ins_enable ctl_tx_parity_err_response Ethernet FCS Stomped Behavior stat_tx_bad_parity

Behavior

 stat_tx_bad_fcs

Behavior
0 0 Core will not stomp FCS, but FCS may have been stomped user logic. stat_tx_bad_parity is asserted if parity errors are detected. 1 stat_tx_bad_fcs  is asserted if the user-generated FCS in the incoming packet is incorrect. Parity errors, which may or may not be present, will not cause a stat_tx_bad_fcs assertion.
0 1 Core will not stomp FCS, but FCS may have been stomped user logic. Same as above. 1 Same as above
1 0 No Same as above. 1 Parity errors, which may or may not be present, will not cause a stat_tx_bad_fcs assertion.
1 1 Yes, if parity errors detected. Same as above. 1 stat_tx_bad_fcs  is asserted if parity errors are detected. 2
  1. There is a limitation such that stat_tx_bad_parity will not be asserted for parity error(s) received on the final clock cycle of an underrun packet (packet that has tx_axis_tuser at the same time as tlast or de-asserts tvalid without tlast) or if an LBUS FIFO underflow event occurs.
  2. There is a limitation such that stat_tx_bad_fcs will not be asserted for parity error(s) received on only the final clock cycle of an underrun packet (packet that has tx_axis_tuser at the same time as tlast or de-asserts tvalid without tlast) or if an LBUS FIFO underflow event occurs. Parity errors received prior to the final clock cycle will still cause stat_tx_bad_fcs to be asserted.