The following tables list the ports for the 10G/25G Ethernet Subsystem with integrated MAC and PCS. These signals are usually found at the wrapper.v hierarchy. These ports are applicable for both the 64-bit integrated MAC+PCS for 25 Gb/s and 10 Gb/s line rates and the low-latency 32-bit integrated MAC + PCS for the 10 Gb/s line rate. When the AXI register interface is included, some of these ports are accessed using the registers instead of the broadside bus.