User Interface - 3.3 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2020-12-16
Version
3.3 English

General purpose I/Os (GPIOs) are provided to control the example design. The user input and output ports are described in the following table.

Table 1. User I/O Ports
Name Size I/O Description
sys_reset 1 I Reset for the core.
gt_ref_clk_p 1 I Differential input clk to GT. This clock frequency should be equal to the GT RefClk frequency mentioned in the Vivado IDE GT Selection and Configuration tab.
Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core option is selected in the Shared Logic tab.
gt_ref_clk_n 1 I Differential input clk to GT. This clock frequency should be equal to the GT RefClk frequency mentioned in the Vivado IDE GT Selection and Configuration tab.
Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core option isselected in the Shared Logic tab.
dclk 1 I Stable/free running input clk to GT. This clock frequency should be equal to the GT DRP clock frequency mentioned in the Vivado IDE GT Selection and Configuration tab.
rx_gt_locked_led_0 1 O Indicates that GT has been locked.
rx_block_lock_led_0 1 O Indicates RX block lock has been achieved.
restart_tx_rx_0 1 I This signal is used to restart the packet generation and reception for the data sanity test when the packet generator and the packet monitor are in idle state.
completion_status 5 O This signal represents the test status/result.
  • 5'd0 Test did not run.
  • 5’d1 PASSED 25GE/10GE CORE TEST SUCCESSFULLY COMPLETED.
  • 5'd2 No block lock on any lanes.
  • 5'd3 Not all lanes achieved block lock.
  • 5'd4 Some lanes lost block lock after achieving block lock.
  • 5'd5 No lane sync on any lanes.
  • 5'd6 Not all lanes achieved sync.
  • 5'd7 Some lanes lost sync after achieving sync.
  • 5'd8 No alignment status or rx_status was achieved.
  • 5'd9 Loss of alignment status or rx_status after both were achieved.
  • 5'd10 TX timed out.
  • 5'd11 No TX data was sent.
  • 5'd12 Number of packets received did not equal the number of packets sent.
  • 5'd13 Total number of bytes received did not equal the total number of bytes sent.
  • 5'd14 A protocol error was detected.
  • 5'd15 Bit errors were detected in the received packets.
  • 5'd31 Test is stuck in reset.
mode_change_* 1 I This port is available only when Runtime Switchable is selected in Vivado IDE and this is used to switch the core speed.
core_speed_* 1 O

This signal indicates the speed with which the core is working:

1’b1 = 10G and 1’b0 = 25G
send_continuous_pkts_* 1 I This port can be used to send continuous packets for board validation.
  • 1'b0 - Sends fixed 20 packets for simulation.
  • 1'b1 - Sends continuous packets for board.
stat_reg_compare 1 O Indicates TX and RX statistics registers comparison status.
  • 1'b1 - Indicates both the TX and RX statistics matched.
  • 1'b0 - Indicates if there is any mismatch between TX and RX statistics.

This output is available when you select Include AXI4-Lite option in the General Tab.
ts_clk 1 I This is the system timer clk input port.
Note: This port is available when you select Enable Timestamping Logic in the GUI Tab-2.
ptp_results_* 1 O The timer comparison signal out to monitor and restrict the tools to optimize the PTP design.
Note: This port is available when you select Enable Timestamping Logic in the GUI Tab-2.