Vitis HLS Flow Overview - 2022.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2022.2 English

Vitis HLS is project based and can contain multiple variations of a project called "solutions" to drive synthesis and simulation. Each solution can target either the Vivado IP flow, or the Vitis Kernel flow.

The Vivado IP flow produces an RTL IP files for use in the Vivado Design Suite, for inclusion in the IP catalog, and for use in block designs of the IP integrator tool. The IP can be used for hardware design in the IP integrator feature of Vivado, or for RTL design.

The Vitis Kernel flow is a structured hardware development environment that lets you quickly expand custom hardware platforms using PL kernels developed in Vitis HLS. Vitis kernels can be used in application acceleration for Data Center applications, or in embedded system design for heterogeneous compute systems.

Vitis HLS implements the solution based on the target flow, default tool configuration, design constraints, and any optimization pragmas or directives you specify. You can use optimization directives to modify and control the implementation of the internal logic and I/O ports, overriding the default behaviors of the tool.