Description
Synthesizes the Vitis HLS project for the active solution.
The command can be executed only in the context of an active solution. The elaborated design in the database is scheduled and mapped onto RTL, based on any constraints that are set.
Syntax
csynth_design [OPTIONS]Options
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-dump_cfg - Write a pre-synthesis control flow graph (CFG).
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-dump_post_cfg - Write a post-synthesis control flow graph (CFG).
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-synthesis_check - Runs a pre-synthesis design rule check, but does not generate RTL.
Examples
Runs Vitis HLS synthesis on the top-level design.
csynth_design