Timeline Trace Viewer - 2022.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2022.2 English

Timeline Trace viewer displays the run time profile of the functions of your design. It is especially useful to see the behavior of dataflow regions after Co-simulation, as there is no need to launch the Vivado logic simulator to view the timeline.

Timeline Trace viewer displays multiple iterations through the various sub-functions of a dataflow region, shows where the functions are starting and ending, and displays the Co-simulation data in tables below the timeline.

The viewer provides basic tools to use while viewing the timeline, such as adding markers, stepping from one marker to the next and measuring the time between markers.

Figure 1. Timeline Trace Viewer

You can generate the Timeline Trace view from RTL Co-simulation. You should enable Dump Trace All, and Enable Channel Profiling options from the Co-Simulation dialog box, or from the Solutions Settings dialog box, and the Co-Sim window.

The Timeline Trace view also shows FIFO channel stall/starve states with Full and Empty markers. In the following figure, you can see the demux FIFO is full, resulting in a stall as highlighted in the timeline. In addition, the mux FIFO is empty and also stalled. The report also shows the loop internal II and latency, and a table at the bottom of the display to show dataflow path status, including performance, total time, stalling time and percentage.

Figure 2. Timeline Full/Empty