By default, the AXI4 master interface starts all read and
write operations from address 0x00000000
. For example, given the following code,
the design reads data from addresses 0x00000000
to 0x000000C7
(50 32-bit words, gives 200 bytes), which represents 50 address values. The design then writes
data back to the same addresses.
void example(int *a){
#pragma HLS INTERFACE mode=m_axi depth=50 port=a
#pragma HLS INTERFACE mode=s_axilite port=return bundle=AXILiteS
int i;
int buff[50];
memcpy(buff,(const int*)a,50*sizeof(int));
for(i=0; i < 50; i++){
buff[i] = buff[i] + 100;
}
memcpy((int *)a,buff,50*sizeof(int));
}
To apply an address offset, use the -offset
option
with the INTERFACE directive, and specify one of the following options:
-
off
: Does not apply an offset address. This is the default. -
direct
: Adds a 32-bit port to the design for applying an address offset. -
slave
: Adds a 32-bit register inside the AXI4-Lite interface for applying an address offset.
In the final RTL, Vitis HLS applies the address offset directly to any read or write address generated by the AXI4 master interface. This allows the design to access any address location in the system.
If you use the slave
option in an AXI interface,
you must use an AXI4-Lite port on the design interface.
Xilinx recommends that you implement the AXI4-Lite interface using the following pragma:
#pragma HLS INTERFACE mode=s_axilite port=return
In addition, if you use the slave
option and
you used several AXI4-Lite interfaces, you must ensure that the AXI master
port offset register is bundled into the correct AXI4-Lite interface.
In the following example, port a
is implemented
as an AXI master interface with an offset and AXI4-Lite interfaces called
AXI_Lite_1
and AXI_Lite_2
:
#pragma HLS INTERFACE mode=m_axi port=a depth=50 offset=slave
#pragma HLS INTERFACE mode=s_axilite port=return bundle=AXI_Lite_1
#pragma HLS INTERFACE mode=s_axilite port=b bundle=AXI_Lite_2
The following INTERFACE directive is required to ensure that the offset register
for port a
is bundled into the AXI4-Lite interface called AXI_Lite_1
:
#pragma HLS INTERFACE mode=s_axilite port=a bundle=AXI_Lite_1