DDS Static Parameters - 2022.2 English

Vitis High-Level Synthesis User Guide (UG1399)
Document ID
UG1399
Release Date
2022-12-07
Version
2022.2 English

The static parameters of the DDS define how to configure the DDS, such as the clock rate, phase interval, and modes. The hls_dds.h header file defines an hls::ip_dds::params_t struct, which sets the default values for the static parameters. To use the default values, you can use the parameterization struct directly with the DDS function.

static hls::DDS< hls::ip_dds::params_t > dds1;
dds1.run(data_channel, phase_channel);

The following table describes the parameters for the hls::ip_dds::params_t parameterization struct.

Recommended: Xilinx highly recommends that you review the DDS Compiler LogiCORE IP Product Guide (PG141) for details on the parameters and values.
Table 1. DDS Struct Parameters
Parameter Description
DDS_Clock_Rate Specifies the clock rate for the DDS output.
Channels Specifies the number of channels. The DDS and phase generator can support up to 16 channels. The channels are time-multiplexed, which reduces the effective clock frequency per channel.
Mode_of_Operation Specifies one of the following operation modes:

Standard mode for use when the accumulated phase can be truncated before it is used to access the SIN/COS LUT.

Rasterized mode for use when the desired frequencies and system clock are related by a rational fraction.
Modulus Describes the relationship between the system clock frequency and the desired frequencies.

Use this parameter in rasterized mode only.
Spurious_Free_Dynamic_Range Specifies the targeted purity of the tone produced by the DDS.
Frequency_Resolution Specifies the minimum frequency resolution in Hz and determines the Phase Width used by the phase accumulator, including associated phase increment (PINC) and phase offset (POFF) values.
Noise_Shaping Controls whether to use phase truncation, dithering, or Taylor series correction.
Phase_Width Sets the width of the following:
  • PHASE_OUT field within m_axis_phase_tdata
  • Phase field within s_axis_phase_tdata when the DDS is configured to be a SIN/COS LUT only
  • Phase accumulator
  • Associated phase increment and offset registers
  • Phase field in s_axis_config_tdata

For rasterized mode, the phase width is fixed as the number of bits required to describe the valid input range [0, Modulus-1], that is, log2 (Modulus-1) rounded up.
Output_Width Sets the width of SINE and COSINE fields within m_axis_data_tdata. The SFDR provided by this parameter depends on the selected Noise Shaping option.
Phase_Increment Selects the phase increment value.
Phase_Offset Selects the phase offset value.
Output_Selection Sets the output selection to SINE, COSINE, or both in the m_axis_data_tdata bus.
Negative_Sine Negates the SINE field at runtime.
Negative_Cosine Negates the COSINE field at runtime.
Amplitude_Mode Sets the amplitude to full range or unit circle.
Memory_Type Controls the implementation of the SIN/COS LUT.
Optimization_Goal Controls whether the implementation decisions target highest speed or lowest resource.
DSP48_Use Controls the implementation of the phase accumulator and addition stages for phase offset, dither noise addition, or both.
Latency_Configuration Sets the latency of the core to the optimum value based upon the Optimization Goal.
Latency Specifies the manual latency value.
Output_Form Sets the output form to two’s complement or to sign and magnitude. In general, the output of SINE and COSINE is in two’s complement form. However, when quadrant symmetry is used, the output form can be changed to sign and magnitude.
PINC[XIP_DDS_CHANNELS_MAX] Sets the values for the phase increment for each output channel.
POFF[XIP_DDS_CHANNELS_MAX] Sets the values for the phase offset for each output channel.