Enabling the Vivado IP Flow - 2022.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2022.2 English

When you select the Vivado IP Flow Target on the Solution Settings dialog box you are configuring Vitis HLS to generate RTL IP files for use in the Vivado Design Suite.

Tip: The flow target can also be enabled using the open_solution -flow_target vivado Tcl command.

The exported Vivado IP can be included in the IP catalog, and used in block designs of the IP integrator tool or in RTL-based design. HLS synthesis transforms your C or C++ code into register transfer level (RTL) code that you can synthesize and implement into the programmable logic region of a Xilinx device. The Vivado IP flow lets you develop and export IP as part of a larger hardware design, and provides hardware drivers to let you perform traditional embedded software design as described in Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400). The Vivado IP flow provides greater flexibility in your design choices, however it leaves the integration and management of the IP to you as well.

The Vivado IP flow can support a wide variety of interface specifications and data transfer protocols, but has default interfaces assigned to function arguments as described in Interfaces for Vivado IP Flow. You can also override the default settings by manually assigning the interface specification for your function argument, using the INTERFACE pragma or set_directive_interface command, to meet the needs of your Vivado design.