AXI4 Master Interface - 2022.2 English

AXI4 memory-mapped (m_axi) interfaces allow kernels to read and write data in global memory (DDR, HBM, PLRAM). Memory-mapped interfaces are a convenient way of sharing data across different elements of the accelerated application, such as between the host and kernel, or between kernels on the accelerator card. Refer to Vitis-HLS-Introductory-Examples/Interface/Memory on Github for examples of some of these concepts.

In the Vitis Kernel flow the m_axi interface is assigned by default to pointer and array arguments. In this flow it supports the following default features:

• Pointer and array arguments are automatically mapped to the m_axi interface
• The default mode of operation is offset=slave in the Vitis flow and should not be changed
• All pointer and array arguments are mapped to a single interface bundle to conserve device resources, and ports share read and write access across the time it is active
• The default alignment in the Vitis flow is set to 64 bytes
• The maximum read/write burst length is set to 16 by default

In both the Vivado IP flow and Vitis kernel flow, the INTERFACE pragma or directive can be used to modify default values as needed. Some customization can help improve design performance as described in Optimizing AXI System Performance.

You can use an AXI4 master interface on array or pointer/reference arguments, which Vitis HLS implements in one of the following modes:

• Individual data transfers
• Burst mode data transfers

With individual data transfers, Vitis HLS reads or writes a single element of data for each address. The following example shows a single read and single write operation. In this example, Vitis HLS generates an address on the AXI interface to read a single data value and an address to write a single data value. The interface transfers one data value per address.

void bus (int *d) {
 static int acc = 0;

 acc += *d;
 *d  = acc;
}

With burst mode transfers, Vitis HLS reads or writes data using a single base address followed by multiple sequential data samples, which makes this mode capable of higher data throughput. Burst mode of operation is possible when you use the C memcpy function or a pipelined for loop. Refer to AXI Burst Transfers for more information.

When this example is synthesized, it results in the interface shown in the following figure.

Figure 1. AXI4 Interface

When using a for loop to implement burst reads or writes, follow these requirements:

• Pipeline the loop
• Access addresses in increasing order
• Do not place accesses inside a conditional statement
• For nested loops, do not flatten loops, because this inhibits the burst operation