Vitis HLS automatically determines the
level of pipelining to use for internal operations. You can use the BIND_OP or
BIND_STORAGE pragmas with the -latency option to
explicitly specify the number of pipeline stages and override the number determined by
Vitis HLS.
RTL synthesis might use the additional pipeline registers to help improve timing issues that might result after place and route. Registers added to the output of the operation typically help improve timing in the output datapath. Registers added to the input of the operation typically help improve timing in both the input datapath and the control logic from the FSM.
You can use the config_op command to pipeline all
instances of a specific operation used in the design that have the same pipeline depth.
Refer to config_op for more information.