The Vivado IDE allows you to specify both
-divide_by and -multiply_by at the same time.
This is an extension to standard Synopsys Design Constraints (SDC) support. This is
particularly convenient for manually defining clocks generated by MMCM or PLL
instances, although Xilinx recommends that you let the engine create these
constraints automatically.
For more information, see Automatically Derived Clocks.
Consider the mmcm0 cell as in Example Three: Duty Cycle Change and Phase Shift with -edges and -edge_shift Options above, and assume that it multiplies the frequency of the master clock by 4/3. The corresponding generated clock definition is:
create_generated_clock -name clk43 -source [get_pins mmcm0/CLKIN] -multiply_by 4 \
-divide_by 3 [get_pins mmcm0/CLKOUT]
If you create a generated clock constraint on the output of an MMCM or PLL, it is better to verify that the waveform definition matches the configuration of the MMCM or PLL.