Supported SDC Commands - 2022.1 English

Note: Because all Xilinx Tcl commands support the -quiet and -verbose options, the following table does not list them.

Table 1. Supported SDC Commands
SDC 1.9	Xilinx SDC	Notes
current_instance [instance_name]	current_instance [instance_name]	The Vivado IDE handles get_ports differently when using read_xdc -cells/-ref or the SCOPED_TO_xxx constraint file property.
expr	expr
list	list	In the Vivado IDE, a Tcl list is also used as an objects container.
set	set
set_hierarchy_separator [separator]	set_hierarchy_separator [separator]
set_units [-capacitance cap_units] [-resistance res_unit] [-time time_unit] [-voltage voltage_units] [-current current_unit] [-power power_unit]	set_units [-capacitance arg] [-resistance arg] [-time arg] [-voltage arg] [-current arg] [-power arg] [-suffix arg] [-digits arg]	The set_units -time cannot change the timing unit in the Vivado IDE.
all_clocks	all_clocks
all_inputs [-level_sensitive] [-edge_triggered] [-clock clock_name]	all_inputs
all_outputs [-level_sensitive] [-edge_triggered] [-clock clock_name]	all_outputs
all_registers	all_registers
[-no_hierarchy]	[-no_hierarchy]
[-clock clock_name]	[-clock args]
[-rise_clock clock_name]	[-rise_clock args]
[-fall_clock clock_name]	[-fall_clock args]
[-cells] [-data_pins] [-clock_pins] [-slave_clock_pins] [-async_pins] [-output_pins] [-level_sensitive] [-edge_triggered] [-master_slave]	[-cells] [-data_pins] [-clock_pins] [-async_pins] [-output_pins] [-level_sensitive]
	[-edge_triggered]
current_design	current_design	In the Vivado IDE, the current design refers to the design loaded in memory, and cannot be changed to another module or entity than the top-level one.
get_cells	get_cells [-hierarchical] [-hsc arg] [-regexp] [-nocase] [-of_objects args] [patterns] [-filter arg] [-match_style arg]
[-hierarchical]
[-hsc separator]
[-regexp]
[-nocase]
-of_objects objects
patterns
get_clocks [-regexp] [-nocase]	get_clocks [-regexp] [-nocase] [patterns] [-filter arg] [-of_objects args] [-match_style arg] [-include_generated_clocks]	The Vivado IDE supports the -of_objects option to query the clock object on the clock tree.
patterns
get_lib_cells	get_lib_cells [-regexp] [-nocase] patterns [-filter arg] [-include_unsupported] [-of_objects args]	In the Vivado IDE, because only one device library can be loaded for a design, it is not necessary to specify the library name when querying the library cells.
[-hsc separator]
[-regexp]
[-nocase]
patterns
get_lib_pins [-hsc separator] [-regexp] [-nocase] patterns	get_lib_pins [-regexp] [-nocase] patterns [-filter arg] [-of_objects args]
get_libs [-regexp] [-nocase] patterns	get_libs [-regexp] [-nocase] [patterns] [-filter arg]
get_nets [-hierarchical] [-hsc separator] [-regexp] [-nocase] -of_objects objects patterns	get_nets [-hierarchical] [-hsc arg] [-regexp] [-nocase] [-of_objects args] [patterns] [-filter arg] [-match_style arg] [-top_net_of_hierarchical_grou p] [-segments] [-boundary_type arg]
get_pins [-hierarchical] [-hsc separator] [-regexp] [-nocase] -of_objects objects patterns	get_pins [-hierarchical] [-hsc arg] [-regexp] [-nocase] [-of_objects args] [patterns] [-leaf] [-filter arg] [-match_style arg]
get_ports [-regexp] [-nocase] patterns	get_ports [-regexp] [-nocase] [patterns] [-filter arg] [-of_objects args] [-match_style arg]
create_clock -period period_value [-name clock_name] [-waveform edge_list] [-add] [source_objects]	create_clock -period arg [-name arg] [-waveform args] [-add] [objects]
create_generated_clock [-name clock_name] -source master_pin [-edges edge_list] [-divide_by factor] [-multiply_by factor] [-duty_cycle percent] [-invert] [-edge_shift shift_list] [-add] [-master_clock clock] [-combinational] source_objects	create_generated_clock [-name arg] [-source args] [-edges args] [-divide_by arg] [-multiply_by arg] [-duty_cycle arg] [-edge_shift args] [-add] [-master_clock arg] [-combinational] objects
group_path	group_path [-name arg] [-weight 1\|2] [-from args] [-to args] [-through args]
[-name group_name]
[-default]
[-weight weight_value]
[-from from_list]
[-rise_from from_list]
[-fall_from from_list]
[-to to_list]
[-rise_to to_list]
[-fall_to to_list]
[-through through_list]
[-rise_through through_list]
[-fall_through through_list]
set_clock_groups [-name name] [-logically_exclusive] [-physically_exclusive] [-asynchronous] [-allow_paths] -group clock_list	set_clock_groups [-name arg] [-logically_exclusive] [-physically_exclusive] [-asynchronous] [-group args]
set_clock_latency	set_clock_latency [-rise] [-fall] [-min] [-max] [-source] [-late] [-early] [-clock args] latency objects
[-rise]
[-fall]
[-min]
[-max]
[-source]
[-late]
[-early]
[-clock clock_list]
delay
object_list
set_clock_sense	set_clock_sense [-positive] [-negative] [-pulse arg] [-stop_propagation] [-clocks args] pins
[-positive]
[-negative]
[-pulse pulse]
[-stop_propagation]
[-clock clock_list]
pin_list
set_clock_uncertainty	set_clock_uncertainty [-from args] [-rise_from args] [-fall_from args] [-to args] [-rise_to args] [-fall_to args] [-setup] [-hold] uncertainty [objects]
[-from from_clock]
[-rise_from rise_from_clock]
[-fall_from fall_from_clock]
[-to to_clock]
[-rise_to rise_to_clock]
[-fall_to fall_to_clock]
[-rise]
[-fall]
[-setup]
[-hold]
uncertainty
[object_list]
set_data_check	set_data_check [-from args] [-to args] [-rise_from args] [-fall_from args] [-rise_to args] [-fall_to args] [-setup] [-hold] [-clock args] value
[-from from_object]
[-to to_object]
[-rise_from from_object]
[-fall_from from_object]
[-rise_to to_object]
[-fall_to to_object]
[-setup]
[-hold]
[-clock clock_object]
value
set_disable_timing	set_disable_timing [-from arg] [-to arg] objects
[-from from_pin_name]
[-to to_pin_name]
cell_pin_list
set_false_path	set_false_path
[-setup]	[-setup]
[-hold]	[-hold]
[-rise]	[-rise]
[-fall]	[-fall]
[-from from_list]	[-from args]
[-to to_list]	[-to args]
[-through through_list]	[-through args]
[-rise_from rise_from_list]	[-rise_from args] [-rise_to args]
[-rise_to rise_to_list]	[-rise_through args]
[-rise_through rise_through_list] [-fall_from fall_from_list]	[-fall_from args] [-fall_to args]
[-fall_to fall_to_list]	[-fall_through args]
[-fall_through fall_through_list]	[-reset_path]
set_input_delay [-clock clock_name] [-clock_fall]	set_input_delay [-clock args] [-clock_fall]	In the Vivado IDE, input delays are not supported on internal pins.
[-level_sensitive]
[-rise]	[-rise]
[-fall]	[-fall]
[-max]	[-max]
[-min]	[-min]
[-add_delay]	[-add_delay]
	[-network_latency_included]
[-network_latency_included ]	[-source_latency_included] delay
[-source_latency_included]	objects
delay_value	[-reference_pin args]
port_pin_list
set_max_delay	set_max_delay
[-rise]	[-rise]
[-fall]	[-fall]
[-from from_list]	[-from args]
[-to to_list]	[-to args]
[-through through_list]	[-through args]
[-rise_from rise_from_list]	[-rise_from args] [-rise_to args]
[-rise_to rise_to_list]	[-rise_through args]
[-rise_through rise_through_list] [-fall_from fall_from_list]	[-fall_from args] [-fall_to args]
[-fall_to fall_to_list]	[-fall_through args]
[-fall_through fall_through_list]	delay
delay_value	[-reset_path]
	[-datapath_only]
set_max_time_borrow delay_value object_list	set_max_time_borrow delay objects
set_min_delay	set_min_delay
[-rise]	[-rise]
[-fall]	[-fall]
[-from from_list]	[-from args]
[-to to_list]	[-to args]
[-through through_list]	[-through args]
[-rise_from rise_from_list]	[-rise_from args] [-rise_to args]
[-rise_to rise_to_list]	[-rise_through args]
[-rise_through rise_through_list] [-fall_from fall_from_list]	[-fall_to args] [-fall_from args]
[-fall_to fall_to_list]	[-fall_through args]
[-fall_through fall_through_list]	delay
delay_value	[-reset_path]
set_multicycle_path	set_multicycle_path
[-setup]	[-setup]
[-hold]	[-hold]
[-rise]	[-rise]
[-fall]	[-fall]
[-start]	[-start]
[-end]	[-end]
[-from from_list]	[-from args]
[-to to_list]	[-to args]
[-through through_list]	[-through args]
[-rise_from rise_from_list]	[-rise_from args] [-rise_to args]
[-rise_to rise_to_list]	[-rise_through args]
[-rise_through rise_through_list] [-fall_from fall_from_list]	[-fall_from args] [-fall_to args]
[-fall_to fall_to_list]	[-fall_through args]
[-fall_through fall_through_list]	path_multiplier
path_multiplier	[-reset_path]
set_output_delay [-clock clock_name] [-clock_fall]	set_output_delay [-clock args] [-clock_fall]	In the Vivado IDE, output delays are not supported on internal pins.
[-level_sensitive]
[-rise]	[-rise]
[-fall]	[-fall]
[-max]	[-max]
[-min]	[-min]
[-add_delay]	[-add_delay]
	[-network_latency_included]
[-network_latency_included ]	[-source_latency_included] delay
[-source_latency_included]	objects
delay_value	[-reference_pin args]
port_pin_list
set_propagated_clock object_list	set_propagated_clock object	In the Vivado IDE, all clocks are propagated clocks by default.
set_case_analysis value port_or_pin_list	set_case_analysis value objects
set_load [-min] [-max]	set_load [-max] [-min]	In the Vivado IDE, the set_load command is relevant for power analysis only.
[-subtract_pin_load]
[-pin_load]
[-wire_load]
value	capacitance
objects	objects
	[-rise]
	[-fall]
set_logic_dc port_list	set_logic_dc objects
set_logic_one port_list	set_logic_one objects
set_logic_zero port_list	set_logic_zero objects
set_operating_conditions	set_operating_conditions	In the Vivado IDE, the set_operating_conditions command: (1) sets the operating conditions for power analysis only; and (2) does not influence the timing reports. The Vivado IDE timing engine is controlled by the config_timing_analysis command. For more information on config_timing_analysis see the Vivado Design Suite Tcl Command Reference Guide (UG835).
[-library lib_name]
[-analysis_type
analysis_type]
[-max max_condition]
[-min min_condition]
[-max_library max_lib]
[-min_library min_lib]
[-object_list objects]
[condition]	[-voltage args]
	[-grade arg]
	[-process arg]
	[-junction_temp arg]
	[-ambient_temp arg]
	[-thetaja arg]
	[-thetasa arg]
	[-airflow arg]
	[-heatsink arg]
	[-thetajb arg]
	[-board arg]
	[-board_temp arg]
	[-board_layers arg]