Hierarchical Names - 2022.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)
Document ID
UG903
Release Date
2022-06-01
Version
2022.1 English

Unless you plan to force Vivado synthesis to keep the complete hierarchy of your design, some or all levels of the hierarchy can be flattened during synthesis. For more information, see the -flatten_hierarchy information at this link in the Vivado Design Suite User Guide: Synthesis (UG901).

Recommended: Use fully resolved hierarchical names in your synthesis constraints where all the hierarchical levels are explicitly written ("/" character) instead of using implicit matching ("*"character). They are more likely to be matching the final netlist names regardless of the hierarchy transformations.

For example, consider the following register located in a sub-level of the design. Elaborated Design Example:

inst_A/inst_B/control_reg

During synthesis (assuming no special optimization is performed on this register), you can get either flat or hierarchical name depending on the tool options or the design structure.

Instance name in a flat netlist:

inst_A/inst_B/control_reg (F)

Instance name in a hierarchical netlist:

inst_A/inst_B/control_reg (H)

There is no obvious difference because the / character is also used to mark flattened hierarchy levels. You will notice the difference when querying the object in memory. The following commands will return the netlist object for F but not H:

% get_cells -hierarchical *inst_B/control_reg
% get_cells inst_A*control_reg

In order to avoid problems related to hierarchical names, Xilinx recommends that you do the following:

  • Use get_* commands without the -hierarchical option.
  • Mark explicitly with the forward-slash (/) character all the levels of hierarchy as they show in the elaborated design view.

Examples without the -hierarchical option:

  • This option works for both flat and hierarchical netlists:
    % get_cells inst_A/inst_B/*_reg
% get_cells inst_*/inst_B/control_reg
  • Another option is:
    % get_cells -hier -filter {NAME =~ inst_A/inst_B/*_reg}
% get_cells -hier -filter {NAME =~ inst_*/inst_B/control_reg}
CAUTION:
(1) Do not attach constraints to hierarchical pins during synthesis for the same reason as explained above for hierarchical cells. (2) Do not attach constraints to nets connecting combinatorial logic operators. They will likely be merged into a LUT and disappear from the netlist.
Recommended: Regularly save your XDC files after editing, and reload the Elaborated design in order to make sure the constraints in memory and the constraints in the XDC files are the same. After running synthesis, load the synthesized design with the same synthesis XDC in memory, and run timing analysis by using the timing summary report.

Some pre-synthesis constraints might no longer apply properly because of the transformations performed by synthesis on the design. To resolve these problems, do the following:

  1. Find the new XDC syntax that applies to the synthesized netlist.
  2. Save the constraints in a new XDC file to be used during implementation only.
  3. Move the synthesis constraints that can no longer be applied to a separate XDC file that will be used for synthesis only.