Use of set_input_delay Command Options - 2022.1 English

The following examples present typical uses of the set_input_delay command options. For additional information about input delay constraint methodology, refer to this link in the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).

Input Delay Example One

This example defines an input delay relative to a previously defined sysClk for both min and max analysis.

> create_clock -name sysClk -period 10 [get_ports CLK0]
> set_input_delay -clock sysClk 2 [get_ports DIN]

Input Delay Example Two

This example defines an input delay relative to a previously defined virtual clock.

> create_clock -name clk_port_virt -period 10
> set_input_delay -clock clk_port_virt 2 [get_ports DIN]

Input Delay Example Three

This example defines a different input delay value for min analysis and max analysis relative to sysClk.

> create_clock -name sysClk -period 10 [get_ports CLK0]
> set_input_delay -clock sysClk -max 4 [get_ports DIN]
> set_input_delay -clock sysClk -min 1 [get_ports DIN]

Input Delay Example Four

To constrain pure combinational paths between I/O ports, an input and output delay must be defined on the I/O ports relative to a previously defined virtual clock.

The example below sets a 5 ns (10 ns - 4 ns - 1 ns) constraint on the combinational path between ports DIN and DOUT:

> create_clock -name sysClk -period 10
> set_input_delay -clock sysClk 4 [get_ports DIN]
> set_output_delay -clock sysClk 1 [get_ports DOUT]

Refer to Combinatorial Delays for further information about constraining combinational paths using the Timing Constraints wizard.

Input Delay Example Five

This example specifies input delay value relative to a DDR clock.

> create_clock -name clk_ddr -period 6 [get_ports DDR_CLK_IN]
> set_input_delay -clock clk_ddr -max 2.1 [get_ports DDR_IN]
> set_input_delay -clock clk_ddr -max 1.9 [get_ports DDR_IN] -clock_fall -add_delay
> set_input_delay -clock clk_ddr -min 0.9 [get_ports DDR_IN]
> set_input_delay -clock clk_ddr -min 1.1 [get_ports DDR_IN] -clock_fall -add_delay

This example creates constraints from data launched by both rising and falling edges of the clk_ddr clock outside the device to the data input of the internal flip-flop that is sensitive to both rising and falling clock edges.

Input Delay Example Six

This example specifies the clock and input delay on the STARTUPE3 internal pins (UltraScale+ devices) to time the paths from STARTUPE3 to the fabric.

> create_generated_clock -name clk_sck -source [get_pins -hierarchical*axi_quad_spi_0/ext_spi_clk] [get_pins STARTUP/CCLK] -edges {3 5 7}
> set_input_delay -clock clk_sck -max 7 [get_pins STARTUP/DATA_IN[*]] -clock_fall
> set_input_delay -clock clk_sck -min 1 [get_pins STARTUP/DATA_IN[*]] -clock_fall

For more information on timing constraints for STARTUPE3, refer to the AXI Quad SPI LogiCORE IP Product Guide (PG153).