Asynchronous Clock Domain Crossings - 2022.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

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2022.1 English

The Timing Constraints wizard analyzes the topology of clock domain crossing (CDC) paths between asynchronous clocks and recommends clock groups or false path constraints whenever it is safe to do so.

Asynchronous clocks are clocks with no known phase relationship, which typically happens when they do not share the same primary clock or do not have a common period. For this reason, slack computation on asynchronous CDC paths is not accurate and cannot be trusted. Due to potentially large skew between asynchronous clocks, the timing quality-of-result can be heavily impacted and prevent proper timing closure if any of the asynchronous CDC paths is timed. You are responsible for adding timing exceptions on these paths, such as set_clock_groups, set_false_path, or set_max_delay -datapath_only to either completely ignore timing analysis or just ignore the clock skew and uncertainty. Also, the design must implement proper CDC circuitry to prevent metastability.

In the Vivado Design Suite, the wizard only identifies flip-flop-based synchronizers for synchronous data and asynchronous reset. For an example of such synchronizers, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

The following figure shows an example of the recommended and non-recommended constraints tables.

Figure 1. Example of Recommended and Non-Recommended Constraints Tables

The columns in both tables display the following information:

Source Clock
This is the clock of the CDC paths start points identified by the wizard.
Destination Clock
This is the clock of the CDC paths endpoints identified by the wizard.
This column shows either the dominant timing exception or the characteristics of the clock relationship when there is no exception.
  • In the Recommended Constraints table, the wizard anticipates that the constraints will be created and displays the new constraint:
    • asynch (clock groups) for the cases where it is safe to ignore timing in both directions, in which case a set_clock_groups constraint is created
    • asynch (false path) when it is only safe to ignore the paths in one direction, in which case a set_false_path constraint is created
  • In the Non-recommended Constraints table, the Timing Constraints wizard displays how the CDC paths are timed before eventually applying a clock group or false path exception:
    • Timed - No Common Primary Clock
    • Timed - No Common Period
    • MaxDelay DataPath for the case where at least 1 path is covered by a set_max_delay -datapath_only constraint and all other paths are covered by false path constraints
The number of CDC path endpoints identified by the wizard.
Synchronized (with ASYNC_REG)
The number of endpoints properly synchronized, with the ASYNC_REG property set to true on all synchronizer flip-flops.
Synchronizer without ASYNC_REG
The number of synchronizers where at least one flip-flop does not have the ASYNC_REG property set to true.
The number of CDC path endpoints where the wizard did not find a synchronizer.
Max Delay Datapath Only
The number of CDC path endpoints that are constrained with a set_max_delay -datapath_only constraint.

The table entries contain cross-probing links whenever applicable. When you click on a number, the corresponding CDC paths are listed in the Paths tab at the bottom of the window. You can select one or several CDC paths and click on the Schematic (F4) button to display the logic of the path(s) in the main Vivado IDE window.