The set_max_delay command and the set_min_delay command
are not typically used to constrain the input or output logic. The input logic between
the input ports and the first level of registers is typically constrained with the
set_input_delay command. This command provides the option to
associate a clock with the input ports.
For the same reason, the output logic between the last level of registers and the output
ports is typically constrained with the set_output_delay command.
However, the set_max_delay command and the
set_min_delay command are typically used to constrain pure
combinational path between primary input ports and primary output port (in-to-out I/O
paths).