As shown in the following figure, the board clock enters the device
through the port sysclk, then propagates through an
input buffer and a clock buffer before reaching the path registers.
- Its period is 10 ns.
- Its duty cycle is 50%.
- Its phase is not shifted.
Corresponding Xilinx Design Constraints (XDC):
create_clock -period 10 [get_ports sysclk]Similar to sysclk, a board clock devclk enters the device through the port ClkIn.
- Its period is 10 ns.
- Its duty cycle is 25%.
- It is phase shifted by 90 degrees.
Corresponding XDC:
create_clock -name devclk -period 10 -waveform {2.5 5} [get_ports ClkIn]The following figure shows a transceiver gt0, which recovers the clock
rxclk from a high speed link on the board. The
clock rxclk has a 3.33 ns period, a 50% duty cycle and
is routed to an MMCM, which generates several compensated clocks for the design.
When defining rxclk on the output driver
pin of GT0, all the generated clocks driven by the MMCM have a common source point,
which is gt0/RXOUTCLK. The slack computation on paths between them uses the proper clock
latency and uncertainty values.
create_clock -name rxclk -period 3.33 [get_pins gt0/RXOUTCLK]
In the following figure, a differential buffer drives the PLL. In such a scenario, the primary clock must only be created on the positive input of the differential buffer. Creating a primary clock on each of the positive/negative inputs of the buffer would result in unrealistic CDC paths. For example:
create_clock -name sysclk -period 3.33 [get_ports SYS_CLK_clk_p]