A Multicycle constraint defined within the same clock domain or between two clocks with the same waveform (no phase-shift) works the same way. See the following figure.
Figure 1. Multicycle Constraint in Single Clock Domain
The default Setup and Hold relationships that are resolved by the Static Timing Analysis (STA) tool are shown in the following figure.
Figure 2. Default Setup and Hold Relationships
The Setup and Hold timing requirements are:
- Setup checkTDatapath(max) < TCLK(t=Period) - TSetup
- Hold checkTDatapath(min) > TCLK(t=0) + THold