Sometimes a timing constraint must be defined between two clock domains that have the same clock period, but a phase-shift between the two clocks. In those cases, it is critical to understand the default setup and hold relationships used by the timing engine. If not carefully adjusted, the phase-shift between two clocks might result in over constraining the logic between the two clock domains.
For example, assume the following:
- The two clocks
CLK1andCLK2have the same waveform. -
CLK2is shifted by +0.3 ns.
The setup relationship is calculated by the timing engine by looking at all the edges on both waveforms and selecting the two edges on the launch and capture clocks that result in the stricter constraint.
Because of the clocks phase-shift, the setup and hold relationships used by the timing engine might not be those expected. See the following figure.
In this example, the setup constraint due to the phase-shift is 0.3 ns. This makes it almost impossible to achieve timing closure. On the other hand, the hold check is -3.7 ns, which is too lenient.
The setup and hold edges must be adjusted to match your intent. This is done by adding a Multicycle constraint with a setup multiplier of two (2):
set_multicycle_path 2 -setup -from [get_clocks CLK1] -to [get_clocks CLK2]This results in moving the capture edge for the setup requirement forward by one cycle. The default edge for the hold is derived from the setup requirement. It does not need to be specified.
In the case of negative phase-shift, as shown in the following figure, between the two clock domains, the launch and capture edges used for the setup and hold checks are similar to those from the previous section (single clock domain, no phase-shift).
For a negative phase-shift, a Multicycle constraint is typically not needed to counter-balance the effect of the phase-shift. An exception occurs if the phase-shift is so large that the clock launch or capture edges must be adjusted to keep realistic setup and hold requirements.