A primary clock is a board clock that enters the design through an input port or a gigabit transceiver output pin (for example, a recovered clock).
A primary clock can be defined only by the create_clock command.
Note: Primary clocks must be defined on a gigabit
transceiver output only for Xilinx
7 series FPGAs. For
UltraScale™
and
UltraScale+™
devices, the timer automatically derives clocks on the
GT output ports.
A primary clock must be attached to a netlist object. This netlist object represents the point in the design from which all the clock edges originate and propagate downstream on the clock tree. In other words, the source point of a primary clock defines the time zero used by the Vivado IDE when computing the clock latency and uncertainty used in the slack equation.
Important: The Vivado IDE ignores all
clock tree delays coming from cells located upstream from the point at which the primary
clock is defined. If you define a primary clock on a pin in the middle of the design,
only part of its latency is used for timing analysis. This can be a problem if this
clock communicates with other related clocks in the design, because the skew, and
consequently the slack, value between the clocks can be inaccurate.
Primary clocks must be defined first, because other timing constraints often refer to them.