Some designs have several operation modes that require the use of different clocks. The selection between the clocks is usually done with a clock multiplexer such as BUFGMUX and BUFGCTRL, or A LUT.
Recommended: Avoid using LUTs in clock trees as much as
possible.
Because these cells are combinatorial cells, the Vivado IDE propagates all incoming clocks to the output. With the Vivado IDE, several timing clocks can exist on a clock tree at the same time, which is convenient for reporting on all the operation modes at once, but is not possible in hardware.
Such clocks are called exclusive clocks. Constrain them as such by using the options of
set_clock_groups:
-
-logically_exclusive -
-physically_exclusive