Syntax for Defining RPM Sets in Verilog

Syntax for Defining RPM Sets in Verilog - 2022.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID

UG903

Release Date

2022-06-01

Version

2022.1 English

The syntax for defining RPM sets as attributes in Verilog is as follows.

U_SET Example


(* U_SET = "uset0", RLOC = "X0Y0" *) FD my_reg (.C(clk), .D(d0), .Q(q0));

HU_SET Example

(* HU_SET = "huset0", RLOC = "X0Y0" *) FD other_reg (.C(clk), .D(d1), .Q(q1));

Recommended: When using H_SET and HU_SET RPMs with Vivado Synthesis, preserve the hierarchical boundary of the module or instance containing the RPMs. This avoids naming collisions between RPMs at the same hierarchical level as a result of hierarchy being dissolved. For further information on hierarchy preservation see the Vivado Design Suite User Guide: Synthesis (UG901).