Single-Bit Register Names - 2022.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

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2022.1 English

By default, the register name is based on the signal name in the RTL, plus the _reg suffix.

For example, for a signal defined as follows in VHDL and Verilog, the instance name generated during the elaboration is wbDataForInputReg_reg:

VHDL: signal wbDataForInputReg : std_logic; Verilog: reg wbDataForInputReg;

The following figure shows the schematic of the register, and its pins. It is possible to define a constraint on the register instance or its pins.

Figure 1. Single-Bit Register in Elaborated Design