Transmit Clocks - 1.1 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
PG371
Release Date
2022-07-21
Version
1.1 English
The transmit clocks in the ILKNF subsystem are as follows:
tx_serdes_clk[5:0]
Transceiver clock for datapath TX lanes. For TX lanes configured in Interlaken mode, tx_serdes_clk[0] is used as the transceiver clock. For TX lanes configured in FEC-only mode, tx_serdes_clk[0] is used for both 50G slices of FEC instance 0, tx_serdes_clk[1] is used for both 50G slices of FEC instance 1, and so on.
tx_alt_serdes_clk[5:0]
TX SerDes alternative clocks. For TX lanes configured in Interlaken mode, tx_alt_serdes_clk[0] is used as the alternative transceiver clock. For TX lanes configured in FEC-only mode, tx_alt_serdes_clk[0] is used for both 50G slices of FEC instance 0, tx_alt_serdes_clk[1] is used for both 50G slices of FEC instance 1, and so on. When used, the frequency of tx_alt_serdes_clk[i] is half of tx_serdes_clk[i], i=0 to 5.