Supported Interlaken Configurations - 1.1 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document ID
PG371
Release Date
2022-07-21
Version
1.1 English

The following shows the supported configurations of the ILKNF subsystem. Support for 106.25 Gb/s (112.84 Gb/s) transceivers is provided using the fabric connectivity of pairs of 53.125 Gb/s (56.42 Gb/s) Interlaken lanes.

Table 1. Summary of Interlaken Configurations
Max Transceiver Rate (Gb/s) Max # Lanes Aggregate BW (Gb/s) AXI Width (Bits) AXI Clock (MHz) Internal Bus Width (Bits) Core Clock (MHz) GT I/F Width (Bits) GT Clock (MHz) Lane Logic Clock (MHz)
56.42 12 677.04 2048 331 1024 662 160 1 352.625 705.25
12 677.04 1536 441 1024 662
10 564.2 2048 276 1024 551
10 564.2 1536 368 1024 551
8 451.36 1536 294 1024 441
8 451.36 1024 441 1024 441
6 338.52 1024 331 512 662
6 338.52 768 441 512 662
4 225.68 768 294 512 441
4 225.68 512 441 512 441
53.125 12 637.5 2048 312 1024 623 80 2 664.0625 664.0625
12 637.5 1536 416 1024 623
10 531.25 2048 260 1024 519
10 531.25 1536 347 1024 519
8 425 1536 278 1024 416
8 425 1024 416 1024 416
6 318.75 1024 312 512 623
6 318.75 768 416 512 623
4 212.5 768 278 512 416
4 212.5 512 416 512 416
28.21 24 677.04 2048 331 1024 662 80 1 352.625 705.25
24 677.04 1536 441 1024 662
18 507.78 2048 249 1024 496
18 507.78 1536 331 1024 496
16 451.36 1536 294 1024 441
16 451.36 1024 441 1024 441
12 338.52 1024 331 512 662
12 338.52 768 441 512 662
10 282.1 1024 277 512 551
10 282.1 768 369 512 551
8 225.68 768 294 512 441
8 225.68 512 441 512 441
6 169.26 512 331 512 441
25.78125 24 618.75 2048 303 1024 605 40 3 644.5313 644.5313
24 618.75 1536 404 1024 605
18 464.0625 2048 228 1024 454
18 464.0625 1536 303 1024 454
16 412.5 1536 269 1024 403
16 412.5 1024 403 1024 403
12 309.375 1024 303 512 605
12 309.375 768 404 512 605
10 257.8125 1024 253 512 504
10 257.8125 768 337 512 504
8 206.25 768 269 512 403
8 206.25 512 403 512 403
6 154.6875 512 303 512 403
12.5 24 300 1024 293 512 586 40 312.5 312.5
24 300 768 391 512 586
18 225 768 293 512 440
12 150 512 293 512 293
  1. An alternative clock from transceiver is required to shrink/widen the internal interface width.
  2. Faster devices support 53.125 Gb/s at 80 bits. Slower devices must use 160 bits with alternate clock.
  3. Faster devices support 25.78125 Gb/s at 40 bits. Slower devices must use 80 bits with alternate clock.
Note: The core clock frequencies listed in the table above are the minimum required to sustain the bandwidth of the Interlaken interface based on the corresponding lane logic clock frequency. Similarly, the AXI clock frequencies are the minimum required based on the corresponding core clock frequency.
Note: The configurations indicating a maximum transceiver rate of 56.42 Gb/s in the table above support frequency scaling by 2.800425% in faster devices to allow support for a maximum transceiver rate of 58 Gb/s. Likewise, configurations listed as 28.21 Gb/s support scaling to 29 Gb/s.
Note: Configurations for transceiver rates not listed in the table are supported by frequency scaling of clocks. You can choose a valid configuration row from the table and scale all frequencies (in that row) by the same factor. The AXI4-Lite processor interface clock does not need to be scaled.
Note: The TX and RX Interlaken paths must be set to the same configuration.